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never stop thinking. preliminary data sheet, ds3, july 2003 wired communications duslic dual channel subscriber line interface concept peb 3264, version 1.4 peb 3265, version 1.5 peb 4264/-2, version 1.1/1.2 peb 4364, version 1.1/1.2 peb 4265/-2, version 1.1/1.2 peb 4365, version 1.2 peb 4266, version 1.2
edition 2003-07-11 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certai n components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but no t limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms a nd conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in lif e-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. abm ? , ace ? , aop ? , arcofi ? , asm ? , asp ? , digitape ? , duslic ? , epic ? , elic ? , falc ? , geminax ? , idec ? , inca ? , iom ? , ipat ? -2, isac ? , itac ? , iwe ? , iworx ? , musac ? , muslic ? , octat ? , optiport ? , potswire ? , quat ? , quadfalc ? , scout ? , sicat ? , sicofi ? , sidec ? , slicofi ? , smint ? , socrates ? , vinetic ? , 10basev ? , 10basevx ? are registered trademarks of infineon technologies ag. 10bases?, easyport?, vdslite? are trademarks of infin eon technologies ag. microsoft ? is a registered trademark of microsoft corporation. linux ? is a registered trademark of linus torvalds. the information in this document is subject to change without notice.
preliminary data sheet revision history: 2003-07-11 ds3 previous version: ds2 page subjects (major chan ges since last revision) title product name corrected to dual channel subscri ber line interface concept all peb 3265 version changed from 1.2 to 1.5 all peb 4264/-2 and peb 4265 /-2: version 1.2 added all peb 4266 version changed from 1.1 to 1.2 all peb 3264 version changed from 1.2 to 1.4 all bit vrtlim renamed to vtrlim all bit vrtlim-m renamed to vtrlim-m all new slics tslic-e and tslic-s added all new slicofi-2 (version 1.5 on ly) package p-tq fp-64-1 added all new package p-vqfn-48-4 for slic -s/-s2, slic-e/-e2 and slic-p added all former chapter 2 "pin descriptions" removed. see updated device data sheets. page 18 ?overview? on page 18 : chapter reworked, tabl es for codec and slic chips added. page 23 ?features? on page 23 : itu-t recommenda tion g.712 added page 25 ?logic symbols? on page 25 : logic symbol for slic -e/-e2 version 1.2 added. page 32 ?block diagram slicofi-2/-2s? on page 32 : block diagrams of slic devices removed. page 33 figure 10 "signal paths ? dc feeding" on page 33 : c ita ( c itb ) renamed to c itaca ( c itacb ). page 38 table 4 "dc char acteristics" on page 38 : v lim changed from 50 v to 72 v. page 42 figure 19 "signal paths ? ac transmission" on page 42 : c ita ( c itb ) renamed to c itaca ( c itacb ). page 50 ?internal balanced ri nging via slics? on page 50 : v drop,rt renamed to v drop,tr , v rt,rms renamed to v tr,rms , v rt0,rms renamed to v tr0,rms page 61 figure 30 "bellcore on-hook call er id physical l ayer transmission" on page 61 : note added. page 61 ?caller id buffer handli ng of slicofi-2? on page 61 : description for listing item (9) changed page 64 ?non linear pro cessor (nlp) in duslic-e/-e2/-p? on page 64 added.
page 66 ?mips requirements for edsp capabilities? on page 66 updated with nlp examples. page 68 ?three-party conferencing in duslic-e/-e2/-p? on page 68 : sentence about multi-party conferencing added page 84 ?hardware and powe r on reset? on page 84 : reset routine duration changed to 1.5 ms. page 85 figure 36 "duslic re set sequence" on page 85 : textual description changed. page 86 table 17 , ?default dc and ac values? on page 86 : l x and l r changed. page 88 ?recommended procedure for re ading the interrupt registers? on page 88 added. page 90 ?power management a nd operating modes? on page 90 : power dissipation values a nd description updated. page 94 ?integrated test and diag nostic functions (itdf)? on page 94 : itdf is now also available for slicofi-2s. page 94 figure 3.8.1.2 "duslic line testing" on page 94 : description on line testing capabi lity modified. page 97 ?using the level mete ring integrator? on page 97 : timing for lm-ok bit added. page 99 figure 44 , ?timing lm-ok bit? on page 99 : 1 ms delay time for slicofi-2 version 1.5 added. page 101 table 20 "kintdc se tting table" on page 101 : description about duslicos setti ngs added below. page 113 ?capacitance measurements? on page 113 : note on offs et calibration added at the end of the chapter. page 116 ?line capacitance measurement s ring and tip to gnd? on page 116 : description of last list item in section "calcula ting parameter values" modified, description in table of section "progr am sequence" modified page 137 chapter 4.2.3 , operation with iom-2 te devices (1.536 mhz) added. page 139 ?tip/ring interface? on page 139 : content removed - see device data sheets for detai led information. page 144 ?sop command? on page 144 : note on empty re gister bits added page 151 register xcr : description for bi t asynch-r changed page 152 register intreg1 , bits hook and gndk : description changes page 154 register intreg2 : reset value changed from 20 h to 4f h , description for bit rstat modified page 167 register bcr1 , bit sleep-en: note added page 170 register bcr2 : description added fot bi ts utdx-src and pdot-dis page 177 register bcr5 , bit dtmf-src: description added page 179 register dscr , bit ptg: description added page 203 ?cop command? on page 203 : note on empty re gister bits added
page 205 table 35 "cram co efficients" on page 205 : ttx slope extended by nibbles 6 and 7 page 207 ?pop command? on page 207 : note on the nece ssity of immediate programming added page 207 ?sequence for pop regist er programming? on page 207 added (because added nlp coefficients) page 208 ?pop register overview? on page 208 : nlp coefficients added page 213 ?pop register description? on page 213 : nlp coefficients added page 233 table 53 "range of deltaplec" on page 233 : "0x80 - no detection" added. page 248 register cis/lec-mode : description added for bit utdx-sum and note on bit 3 added. page 258 ?recommended nlp co efficients? on page 258 added page 266 ?sop command? on page 266 : note on empty re gister bits added page 273 register xcr: descripti on for bit asyn ch-r changed page 278 register lmres1 : bits added. page 278 register lmres2 : bits added. page 287 register bcr1 : bits added. page 295 register dscr , bit ptg: description added page 297 register lmcr1 : bits added. page 299 register lmcr2 : bits added. page 301 register lmcr3 : bits added. page 315 ?cop command? on page 315 : note on empty re gister bits added page 318 table 73 "cram co efficients" on page 318 : ttx slope extended by nibbles 6 and 7 page 325 ?electrical characteristics? on page 325 : slic and slicofi-2x data removed - for detailed informat ion see device data sheets. page 326 table 76 , ?ac transmission? on page 326 : symbol v rt renamed to v tr page 331 ac transmission characteri stics: values for dist ortion and associated figures changed page 342 ?input/output wavefo rm for ac tests? on page 342 added. page 344 pcm interface timings ?single-clocking mode? on page 344 and ?double-clocking mode? on page 346 : fsc hold time ( t fsc_h ) renamed to fsc hold time 1 ( t fsc_h1 ), fsc hold time 2 ( t fsc_h2 ) added, formula of max. value for tca/b delay time off ( t dtcoff ) modified page 349 iom-2 interface timings ?single-clocking mode? on page 349 and ?double-clocking mode? on page 351 : fsc hold time ( t fsc_h ) renamed to fsc hold time 1 ( t fsc_h1 ), fsc hold time 2 ( t fsc_h2 ) added, parameters and timing of pin du modified period pclk ( t pclk ) for double clocking: formula for typ. value modified.
page 353 figure 90 , ?internal (balanced and unbala nced) ringing with slic-p? on page 353 : pin ts2/cs changed to ts2/cs , illustration of connection between pins c3 and io2a modified , slic supply voltages added, arrangement of diodes d1 and d2 modified. page 355 table 79 , ?external components in app lication circuit duslic-e/-e2/- s/-s2/-p? on page 355 : tolerance of r stab and r prot changed to 1%, footnote added. page 357 figure 92 , ?external unbalanced ringing wi th slic-e/-e2 or slic-s/- s2? on page 357 : pin ts2/cs changed to ts2/cs , illustration of connection between pins c3 and io2a modified,slic supply voltages added page 359 figure 94 , ?external unb. ringing (long loops) with slic-e/-e2 or slic-s/-s2? on page 359 : pin ts2/cs changed to ts2/cs , illustration of connection between pins c3 and io2 a modified, slic supply voltages added page 363 figure 97 , ?slic-s/-s2, slic-e/-e2, sl ic-p (peb 426x)? on page 363 : note on slic clo ckwise pin counting added, security wa rning for all slic packages added
duslic table of contents page preliminary data sheet 7 ds3, 2003-07-11 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.2 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.3 logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.1.1 basic functions of all dusl ic chip sets . . . . . . . . . . . . . . . . . . . . . . . . 29 2.1.2 additional functions of the duslic-e/- e2/-p chip sets . . . . . . . . . . . . 30 2.2 block diagram slicofi-2/-2s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3 dc feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.1 dc characteristic feeding zo nes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.2 constant current zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.3 resistive zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3.4 constant voltage zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.3.5 programmable voltage an d current range: dc charac teristics . . . . . 38 2.3.6 slic power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3.7 necessary voltage reserve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.3.8 extended battery feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4 ac transmission characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.4.1 transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.4.2 receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.4.3 matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5 ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.5.1 ringer load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.5.2 ring trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.5.3 ringing methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.5.4 duslic ringing options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.5.5 internal balanced ri nging via slics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.5.6 internal unbalanced ringing with slic-p . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.7 external unbalanced ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.6 signaling (supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.7 metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.7.1 metering by 12/16 khz sinusoidal bursts . . . . . . . . . . . . . . . . . . . . . . . 54 2.7.2 metering by polarity reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.7.2.1 soft reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.8 duslic enhanced signal proce ssing capabilities . . . . . . . . . . . . . . . . . . 56 2.8.1 dtmf generation and detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.8.2 caller id generation in duslic-e/-e2/-p . . . . . . . . . . . . . . . . . . . . . . . 59 2.8.2.1 caller id buffer handling of slicofi-2 . . . . . . . . . . . . . . . . . . . . . . . 61 2.8.3 line echo cancellation in duslic-e/-e2/-p . . . . . . . . . . . . . . . . . . . . . 63 2.8.4 non linear processor (nlp) in duslic-e/- e2/-p . . . . . . . . . . . . . . . . . 64 2.8.5 universal tone detection in duslic-e/-e2/-p . . . . . . . . . . . . . . . . . . . 65
duslic table of contents page preliminary data sheet 8 ds3, 2003-07-11 2.8.6 mips requirements for edsp capabilities . . . . . . . . . . . . . . . . . . . . . . 66 2.9 message waiting indication in duslic-e/-e2/-p . . . . . . . . . . . . . . . . . . . . 67 2.10 three-party conferencing in duslic-e/-e2/-p . . . . . . . . . . . . . . . . . . . . . 68 2.10.1 conferencing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.11 16 khz mode on pcm highways . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.1 overview of all duslic operat ing modes . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.2 operating modes for the du slic-s/-s2/-se/-se2 chip set . . . . . . . . . . . 78 3.3 operating modes for the du slic-e/-e2/-es/-es2 chip set . . . . . . . . . . . 80 3.4 operating modes for the duslic -p chip set . . . . . . . . . . . . . . . . . . . . . . 82 3.5 reset mode and reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.5.1 hardware and power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.5.2 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.6 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.6.1 recommended procedure fo r reading the interrupt re gisters . . . . . . . 88 3.7 power management and operat ing modes . . . . . . . . . . . . . . . . . . . . . . . 90 3.7.1 slicofi-2x power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.7.2 slic power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.7.2.1 power down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.7.2.2 active modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.7.2.3 ringing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.8 integrated test and di agnostic functions (itd f) . . . . . . . . . . . . . . . . . . . 94 3.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.8.1.1 conventional line testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.8.1.2 duslic line testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.8.2 diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.8.2.1 line test capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.8.2.2 integrated signal sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.8.2.3 result register data forma t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.8.2.4 using the level metering in tegrator . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.8.2.5 dc level metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.8.2.6 ac level meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.8.2.7 level meter threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.8.2.8 current offset error compensation . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.8.2.9 loop resistance measuremen ts . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.8.2.10 line resistance tip/gnd and ring/gnd . . . . . . . . . . . . . . . . . . . . 113 3.8.2.11 capacitance measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.8.2.12 line capacitance measurements ring and tip to gnd . . . . . . . . . 116 3.8.2.13 foreign- and ri ng voltage measurements . . . . . . . . . . . . . . . . . . . 116 3.9 signal path and test l oops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.9.1 ac test loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.9.2 dc test loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
duslic table of contents page preliminary data sheet 9 ds3, 2003-07-11 4 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.1 pcm interface with a serial microcontroller interface . . . . . . . . . . . . . . . 122 4.1.1 pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.1.2 control of the active pcm channels . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.1.3 serial microcontroller interfac e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.2 the iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.2.1 iom-2 interface monitor tran sfer protocol . . . . . . . . . . . . . . . . . . . . . 133 4.2.2 slicofi-2x identification command . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.2.3 operation with iom-2 te devices (1.536 mh z) . . . . . . . . . . . . . . . . . 137 4.3 tip/ring interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5 slicofi-2x command structure and programming . . . . . . . . . . . . . 140 5.1 overview of commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5.2 slicofi-2 command structur e and programming . . . . . . . . . . . . . . . . . 144 5.2.1 sop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.2.1.1 sop register overvi ew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.2.1.2 sop register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 5.2.2 cop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 5.2.2.1 cram programming ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 5.2.3 pop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 5.2.3.1 sequence for pop register programming . . . . . . . . . . . . . . . . . . . 207 5.2.3.2 pop register overvi ew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 5.2.3.3 pop register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 5.2.3.4 recommended nlp coefficient s . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 5.2.4 iom-2 interface command/indi cation byte . . . . . . . . . . . . . . . . . . . . . 260 5.2.5 programming examples of the slicofi-2 . . . . . . . . . . . . . . . . . . . . . 262 5.2.5.1 microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 5.2.5.2 iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 5.3 slicofi-2s command structur e and programming . . . . . . . . . . . . . . . 266 5.3.1 sop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 5.3.1.1 sop register overvi ew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 5.3.1.2 sop register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 5.3.2 cop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 5.3.2.1 cram programming ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 5.3.3 iom-2 interface command/indi cation byte . . . . . . . . . . . . . . . . . . . . . 320 5.3.4 programming examples of the slicofi-2s . . . . . . . . . . . . . . . . . . . . 322 5.3.4.1 microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 5.3.4.2 iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 6.1 ac transmission duslic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 6.1.1 frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 6.1.2 gain tracking (receive or transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . 335
duslic table of contents page preliminary data sheet 10 ds3, 2003-07-11 6.1.3 group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 6.1.4 out-of-band signals at an alog output (receive) . . . . . . . . . . . . . . . . 336 6.1.5 out-of-band signals at analog input (trans mit) . . . . . . . . . . . . . . . . . 338 6.1.6 total distortion measured with sine wave . . . . . . . . . . . . . . . . . . . . . 339 6.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 6.3 duslic power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 6.4 duslic timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 6.4.1 input/output waveform for ac tests . . . . . . . . . . . . . . . . . . . . . . . . . . 342 6.4.2 mclk/fsc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 6.4.3 pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 6.4.3.1 single-clocking mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 6.4.3.2 double-clocking mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 6.4.4 microcontroller interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 6.4.5 iom-2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 6.4.5.1 single-clocking mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 6.4.5.2 double-clocking mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 7 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 7.1 internal ringing (balanced/unbal anced) . . . . . . . . . . . . . . . . . . . . . . . . . 352 7.1.1 circuit diagrams internal ringing (bal anced & unbalanced) . . . . . . . 353 7.1.2 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 7.2 external unbalanced ringing with duslic -e/-e2/-s/-s2/-p . . . . . . . . . . 356 7.2.1 circuit diagrams external unbalanced ringing . . . . . . . . . . . . . . . . . . 357 7.3 duslic layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 9 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 10 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
duslic list of figures page preliminary data sheet 11 ds3, 2003-07-11 figure 1 duslic chip set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 2 logic symbol: slicofi-2/-2 s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 3 logic symbol: slic-s /slic-s2 (v1.1, v1.2), sl ic-e/slic-e2 (v1.1) 26 figure 4 logic symbol: slic-e/slic- e2 (v1.2) . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5 logic symbol: slic-p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 6 logic symbol: tslic-s/tsli c-e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7 line circuit functions in the duslic-s/- s2 . . . . . . . . . . . . . . . . . . . . . 31 figure 8 line circuit functions in the duslic-e/- e2/-p . . . . . . . . . . . . . . . . . . 31 figure 9 block diagram: slicofi-2/-2s (peb 3265, peb 3264) . . . . . . . . . . . 32 figure 10 signal paths ? dc feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 11 dc feeding characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 12 constant current zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 13 resistive zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 14 constant voltage zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 15 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 16 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 17 ttx voltage reserve schema tic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18 dc feeding characterist ics (acth, actr) . . . . . . . . . . . . . . . . . . . . 41 figure 19 signal paths ? ac transmissi on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 20 signal flow in voice cha nnel (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 21 nyquist diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 22 typical ringer loads of 1 and 5 ren used in usa. . . . . . . . . . . . . . . 45 figure 23 external ringing zero crossing synchronization . . . . . . . . . . . . . . . . 49 figure 24 balanced ringing via slic-e/-e2, sl ic-s and slic-p . . . . . . . . . . . . 50 figure 25 unbalanced ringi ng signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 26 teletax injection and metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 27 soft reversal (example for open loop) . . . . . . . . . . . . . . . . . . . . . . . 55 figure 28 duslic ac signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 29 duslic edsp signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 30 bellcore on-hook caller id physical layer transmission . . . . . . . . . . 61 figure 31 line echo cancellation unit block diagram . . . . . . . . . . . . . . . . . . . . 63 figure 32 utd functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 33 mwi circuitry with glow la mp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 34 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 35 conference block for one duslic channel . . . . . . . . . . . . . . . . . . . . 69 figure 36 duslic reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 37 reading interrupt r egisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 38 typical slic powe r dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 39 duslic line testin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 40 level metering block diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 41 single measurement sequence (ac & dc level metering) . . . . . . . . 97 figure 42 continuous measurement sequence (d c level metering) . . . . . . . . . 98
duslic list of figures page preliminary data sheet 12 ds3, 2003-07-11 figure 43 continuous measurement sequence (a c level metering) . . . . . . . . . 98 figure 44 timing lm-ok bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 45 example resistance measur ement . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 46 differential resistance me asurement . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 47 capacitance measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 48 foreign voltage measurem ent principle . . . . . . . . . . . . . . . . . . . . . . 117 figure 49 ac test loops duslic-e /-e2/-p/-es/-es2 . . . . . . . . . . . . . . . . . . . . 119 figure 50 ac test loops duslic-s/-s2/-se/-se2 . . . . . . . . . . . . . . . . . . . . . . 120 figure 51 dc test loops duslic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 52 general pcm interface timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 53 setting the slopes in register pcmc1 . . . . . . . . . . . . . . . . . . . . . . . 125 figure 54 serial microcontroller interface write a ccess . . . . . . . . . . . . . . . . . . 128 figure 55 serial microcontroller interface read a ccess . . . . . . . . . . . . . . . . . . 128 figure 56 iom-2 i/f timing for up to 16 voice channels (p er 8 khz frame) . . 130 figure 57 iom-2 interface timing (dcl = 4096 khz, per 8 khz frame) . . . . . . 131 figure 58 iom-2 interface timing (dcl = 2048 khz, per 8 khz frame) . . . . . . 131 figure 59 iom-2 interface monitor transfer protocol . . . . . . . . . . . . . . . . . . . . 133 figure 60 state diagram of the slicofi-2x monitor transmitter . . . . . . . . . . . 135 figure 61 state diagram of the slicofi-2x monitor receiver . . . . . . . . . . . . . 136 figure 62 pcm/mc mode used for iom-2 te inte rface at 1.536 mhz. . . . . . . . 138 figure 63 example for switching between differe nt ring offset volt ages . . . . 187 figure 64 example for utd recognition timing . . . . . . . . . . . . . . . . . . . . . . . . 256 figure 65 example for utd tone en d detection timing . . . . . . . . . . . . . . . . . . 258 figure 66 waveform of programming example sop-write to channel 0 . . . . . 262 figure 67 waveform of programming example sop read from chann el 0 . . . 263 figure 68 example for switching between differe nt ring offset volt ages . . . . 303 figure 69 waveform of programming example sop write to channe l 0 . . . . . 322 figure 70 waveform of programming example sop read from chann el 0 . . . 322 figure 71 signal definitions transmit, receive . . . . . . . . . . . . . . . . . . . . . . . . . 325 figure 72 overload compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 figure 73 frequency response transm it . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 figure 74 frequency response receiv e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 figure 75 gain tracking receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 figure 76 gain tracking tran smit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 figure 77 group delay distortion receive and transmit. . . . . . . . . . . . . . . . . . 336 figure 78 out-of-band signals at analog output (receive) . . . . . . . . . . . . . . . 337 figure 79 out-of-band signals at analog input (t ransmit) . . . . . . . . . . . . . . . . 338 figure 80 total distortion transmit (lx = 0 dbr) . . . . . . . . . . . . . . . . . . . . . . . . 339 figure 81 total distortion receive (lr = ?7 dbr) . . . . . . . . . . . . . . . . . . . . . . . 339 figure 82 total distortion receive (lr = 0 dbr) . . . . . . . . . . . . . . . . . . . . . . . . 340 figure 83 waveform for ac test s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 figure 84 mclk/fsc-timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
duslic list of figures page preliminary data sheet 13 ds3, 2003-07-11 figure 85 pcm interface timing ? single-clocking mode . . . . . . . . . . . . . . . . . 344 figure 86 pcm interface timing ? double-clocking mode . . . . . . . . . . . . . . . . 346 figure 87 microcontroller interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 figure 88 iom-2 interface timing ? single-clocking mode . . . . . . . . . . . . . . . . 349 figure 89 iom-2 interface timing ? double-clocki ng mode . . . . . . . . . . . . . . . 351 figure 90 internal (balanced and unbalanced) ri nging with slic-p . . . . . . . . . 353 figure 91 internal (balanced) ri nging with slic-e/-e2 or sl ic-s/-s2 . . . . . . . 354 figure 92 external unbalanced ringing with slic-e/-e2 or slic-s /-s2. . . . . . 357 figure 93 external unbalanced ringi ng with slic-p . . . . . . . . . . . . . . . . . . . . 358 figure 94 external unb. ring ing (long loops) with slic-e/-e2 or slic-s/-s2 359 figure 95 external unbalanced ringing (long loops) with slic -p . . . . . . . . . 360 figure 96 duslic layout recommenda tion . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 figure 97 slic-s/-s2, slic-e/-e2, slic-p (peb 42 6x) . . . . . . . . . . . . . . . . . . 363 figure 98 slic-s/-s2, slic-e/-e2, slic-p (peb426x ). . . . . . . . . . . . . . . . . . . 364 figure 99 tslic-s (peb 4364) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 figure 100 tslic-e (peb 4365) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 figure 101 slicofi-2x (peb 3265, peb 3264) . . . . . . . . . . . . . . . . . . . . . . . . . 367 figure 102 slicofi-2x (peb 3265, peb 3264) . . . . . . . . . . . . . . . . . . . . . . . . . 368
duslic list of tables page preliminary data sheet 14 ds3, 2003-07-11 table 1 codec feature overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 2 slic feature overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3 duslic chip sets presente d in this data sheet . . . . . . . . . . . . . . . . . 20 table 4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5 ringing options with slic-s, slic-e/-e2 and slic-p . . . . . . . . . . . . 47 table 6 performance characteri stics of the dtmf decoder algorithm . . . . . . 58 table 7 fsk modulation characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 8 mips requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 9 conferencing modes: receiv e channels. . . . . . . . . . . . . . . . . . . . . . . 69 table 10 conferencing modes: transm it channels . . . . . . . . . . . . . . . . . . . . . . 70 table 11 possible modes in pcm/ c interface mode: receiv e channels . . . . . 72 table 12 possible modes in pcm/ c interface mode: transmit channels . . . . 72 table 13 overview of all duslic operating modes . . . . . . . . . . . . . . . . . . . . . . 74 table 14 duslic-s/-s2/-se/-se2 operating modes . . . . . . . . . . . . . . . . . . . . . 78 table 15 duslic-e/-e2/-es/-es2 operating modes . . . . . . . . . . . . . . . . . . . . . 80 table 16 duslic-p operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 17 default dc and ac values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 18 level metering result valu e range . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 19 selecting dc level meter pa th . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 20 kintdc setting table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 21 nsamples setting table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 22 level meter results with and without integrator function . . . . . . . . . 103 table 23 selecting ac level meter pa th . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 24 kintac setting table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 25 ktg setting table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 26 threshold setting table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 27 measurement input selectio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 28 slicofi-2x pcm interface configuration . . . . . . . . . . . . . . . . . . . . . 124 table 29 active pcm channel config uration bits . . . . . . . . . . . . . . . . . . . . . . 126 table 30 iom-2 time slot assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 31 m2, m1, m0: general operating mode . . . . . . . . . . . . . . . . . . . . . . . 141 table 32 valid dtmf keys (bit dtmf-key4 = 1) . . . . . . . . . . . . . . . . . . . . . . 155 table 33 dtmf keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 34 typical usage for the th ree ring offsets . . . . . . . . . . . . . . . . . . . . . . 187 table 35 cram coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 36 cram programming ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 37 range of t pow-lpf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 38 range of twist acc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 39 range of t pow-lps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 table 40 range of powbn-lev-x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 table 41 range of powbn-lev-r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 42 range of tbn-inc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
duslic list of tables page preliminary data sheet 15 ds3, 2003-07-11 table 43 range of tbn-dec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 44 ranges of gdtmf[db] dep endent on ?e? . . . . . . . . . . . . . . . . . . . . . 224 table 45 example for dtmf-gain calculation . . . . . . . . . . . . . . . . . . . . . . . . 224 table 46 range of powbn-max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 47 range for deltabn-adj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 48 range of erllre-min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 49 range of erllre-est . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 50 range of ssd-lev-x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 table 51 range of powlecr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 table 52 range of ssd-lev-r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 53 range of deltaplec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 table 54 range of deltasd-lev-bn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 table 55 examples for deltaq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 table 56 range of deltasd-lev-re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 table 57 ranges of glec-xi[db] de pendent on ?e? . . . . . . . . . . . . . . . . . . . . 237 table 58 example for lec-gain-xi calculation . . . . . . . . . . . . . . . . . . . . . . . 237 table 59 range of tsd-ot-dt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 table 60 ranges of glec-ri[db] de pendent on ?e? . . . . . . . . . . . . . . . . . . . . 239 table 61 example for lec-gain-ri calculation . . . . . . . . . . . . . . . . . . . . . . . 239 table 62 range of terl-lin-lp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 63 ranges of glec-x0[db] dependent on ?e? . . . . . . . . . . . . . . . . . . . . 241 table 64 example for lec-gain-x0 calculation . . . . . . . . . . . . . . . . . . . . . . . 241 table 65 range of terl-lec-lp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 66 range of deltact-lev-re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 67 range of levcis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 table 68 utd inband/outband attenuat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 table 69 recommended nlp coefficien ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 table 70 m2, m1, m0: general operating mode . . . . . . . . . . . . . . . . . . . . . . . 260 table 71 dtmf keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 table 72 typical usage for the th ree ring offsets . . . . . . . . . . . . . . . . . . . . . . 303 table 73 cram coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 table 74 cram programming ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 table 75 m2, m1, m0: general operating mode . . . . . . . . . . . . . . . . . . . . . . . 320 table 76 ac transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 table 77 group delay absolute values: signal level 0 dbm0 . . . . . . . . . . . . . 336 table 78 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 table 79 external components in applicati on circuit duslic-e /-e2/-s/-s2/-p 355
duslic preliminary data sheet 16 ds3, 2003-07-11 preface this preliminary data sheet describes the fa mily of duslic chip sets. each chip set comprises a dual channel slicofi-2x codec and two single- or one dual-channel slics. for more duslic related docume nts, please see our webpage at http://www.infineon.com/duslic. to simplify matters, the following synonyms are used: slicofi-2x: synonym used for all code c versions slicofi-2/-2s slic: synonym used for all slic versio ns slic-s/-s2, tslic-s, slic-e/-e2, tslic-e and slic-p. attention: the tslic-s (peb 4364) a nd tslic-e (peb 4365) chips are dual channel versions of the slic-s (p eb 4364) and slic-e (peb 4365) with identical technical specifications for each channel. therefore whenever slic-s or slic-e are mentioned in the specification, also tslic-s and tslic-e can be deployed. organization of this document chapter 1 , overview a general description of the chip set, the key features, an d some typical applications. chapter 2 , functional description the main functions of the chip set are presented with fu nctional block diagrams. chapter 3 , operational description a brief description of the operating modes, the power management, and the integrated test and diagnostic functions. chapter 4 , interfaces connection information incl uding standard iom-2 and pcm interface timing frames and pins. chapter 5 , slicofi-2x command structure and programming a general description of the slicofi-2x command structure. chapter 6 , electrical characteristics parameters, symbols, and limit values are prov ided for the chip set. chapter 7 , application circuits external components and la yout recommendations are id entified. illustrations of balanced ringing, unba lanced ringing, and protec tion circuits are included. chapter 8 , package outlines illustrations and dimensions of the package outlines.
duslic preliminary data sheet 17 ds3, 2003-07-11 chapter 9 , terminology list of abbreviations an d descriptions of symbols. chapter 10 , index
duslic overview preliminary data sheet 18 ds3, 2003-07-11 1overview duslic is a family of communications chip sets. each chip set comprises one dual-channel slicofi-2x codec and two sing le-channel slics or one dual-channel tslic. it is a highly flexible codec/slic solution for an analog line circuit and is easily programmable via software. users can now serve different markets with a single hardware design that meet s all standards worldwide. the key benefits of the duslic family include: integrated dsp features line echo cancel lation (up to 8 ms) dtmf caller-id full v.90 performance integrated ringing balanced ringing up to 85 vrms unbalanced ringing up to 50 vrms full support for external ringing smallest footprint only 121 mm2 per channel minimum external components system features test & diagnostic functions (complete ac & dc) time-slot assignment on two pcm highways proven technology a single hardware design meets/ exceeds worldwide requirements. 15+ years experience. several million lines deployed worldwide.
duslic overview preliminary data sheet 19 ds3, 2003-07-11 the duslic family allows any combinati on of the codec and sl ic chips shown in table 1 and table 2 . table 1 codec feature overview features slicofi-2 slicofi-2s number of voice channels 2 2 dtmf detection yes no line echo cancellation (up to 8 ms) yes no caller-id generation yes no integrated test and diagnostics (linetesting) yes yes modem (v.90) transmission yes yes modem tone de tection yes no metering pulses (ttx) up to 2.5 vrms up to 1.2 vrms pcm/serial controller interface yes yes iom2 interface yes yes internal ring support yes yes external ringing support yes yes supply voltage 3.3 v 3.3 v table 2 slic feature overview features slic-s/ tslic-s 1) slic-s2 2) slic-e/ tslic-e 3) slic-e2 4) slic-p maximum dc feeding 32ma 50ma 32ma 50ma 32ma maximum ringing voltage (balanced) 45 vrms 45 vrms 85 vrms 85 vrms 85 vrms maximum ringing voltage (unbalanced) ????50vrms longitudinal balance 53db 60db 53db 60db 53db supply voltages (negative/positive) 2/1 2/1 2/1 2/1 3/0 supply voltage 3.3 v... 5v 3.3 v... 5v 5.0v 5.0v 3.3v external ring support yes yes yes yes yes
duslic overview preliminary data sheet 20 ds3, 2003-07-11 to allow the most cost effective and feat ure optimized design the following table presents the available slic and codec combinations. the ch oice of different combinations meets world wide design requirements. the duslic chip sets presente d in this data sheet are diff erentiated in terms of the dsp features and ringing voltage : ? duslic-s (standard) ? duslic-se (standard codec, enhanced slic) ? duslic-es (enhanced c odec, standard slic) ? duslic-e (enhanced) ? duslic-p (power management). technology 90 v 90 v 170 v 170 v 170 v on-hook transmission yes yes yes yes yes current limitation 105 ma 105 ma 105 ma 105 ma 60/90 ma target application low cost cpe linecard (external ringing) cpe linecard low power cpe 1) same specifications as slic-s, but two voice channels 2) chip marked as peb 4264 ? packaging unit labeled with peb 4264-2. 3) same specifications as slic-e, but two voice channels 4) chip marked as peb 4265 ? packaging unit labeled with peb 4265-2. table 3 duslic chip sets pres ented in this data sheet chip set duslic-s/ -s2 duslic- se/-se2 duslic- es/-es2 duslic-e/ -e2 duslic-p marketing name slicofi-2s/ slic-s/-s2 (tslic-s) 1) 1) single channel slic-s or dual channel tslic-s package slicofi-2s/ slic-e/-e2 (tslic-e) 2) 2) single channel slic-e or dual channel tslic-e package slicofi-2/ slic-s/-s2 (tslic-s) 1) slicofi-2/ slic-e/-e2 (tslic-e) 2) slicofi-2/ slic-p product id peb 3264/ peb 4264/-2 (peb 4364) peb 3264/ peb 4265/-2 (peb 4365) peb 3265/ peb 4264/-2 (peb 4364) peb 3265/ peb 4265/-2 (peb 4365) peb 3265/ peb 4266 table 2 slic feature overview (cont?d) features slic-s/ tslic-s 1) slic-s2 2) slic-e/ tslic-e 3) slic-e2 4) slic-p
duslic overview preliminary data sheet 21 ds3, 2003-07-11 for both the duslic-s and duslic-e th ere are also long-haul versions, offering increased longitudinal balance (60 db) : ? duslic-e2 (using slic-e2) ? duslic-s2 (using slic-s2) usage of codecs and slics the duslic-s and duslic-s2 chip sets use the slicofi-2s (peb 3264) codec offering full basic pots functionality, includi ng programmable ac and dc characteristics, integrated ringing and integrated test & diagnostic functions (itdf) etc. the duslic-e, duslic-e2, and duslic-p chip sets use the same slicofi-2 (peb 3265) codec with full ed sp (enhanced digital signal pr ocessor) features such as dtmf detection, caller id g eneration, universal tone dete ction (utd) and line echo cancellation (lec). these codecs (slicofi-2 and slicofi-2s) are manufactured using an advanced 0.35 m 3.3 v cmos process. the main criteria for choosing the appropriate slic device, are the ringing voltage and longitudinal balance. slic-s and slic-s2 offer bala nced ringing (up to 45 vrms) slic-e and slic-e2 offer bala nced ringing (up to 85 vrms) slic-p offers both balanced (85v rms) and unbalanced ringing (50 vrms) note: the above ring voltages are achievable with 20 vdc offset. smaller dc offset will increase the maximum achievable ring voltage the slic-s2 and slic-e2 are optimized for lo nghaul applications, and offer a minimum of 60 db longitudinal balance. all infineon slics are manu factured in our well-proven 90 v and 170 v smart power technology (spt) processes. dual-channel slics : tslic-s & tslic-e the tslic-s (peb 4364) and tslic-e (peb 4365) chips are dual channel versions of the slic-s (peb 4264) and sl ic-e (peb 4265) with identical techni cal specifications for each channel. therefore when ever slic-s or slic-e are mentioned in th is and other duslic documentation, also tslic- s and tslic-e can be deployed. duslic architecture unlike traditional designs, duslic splits the slic functi on into high-voltage slic functions and low-volt age slic functions. the low-voltage function s are handled in the slicofi-2x device. the parti tioning of the functions is shown in figure 1 .
duslic overview preliminary data sheet 22 ds3, 2003-07-11 for further information see chapter 2.1 . figure 1 duslic chip set ezm14034 slicofi-2x hv slic functions lv slic functions codec filter functions voltage feeding programmable dc feeding filtering transversal current ring generation a-law/-law companding sensing supervision programmable gain longitudinal current teletax generation programmable frequency sensing teletax notch filter impedance matching overload protection ring trip detection trans-hybrid balance battery switching ground key detection dtmf generation ring amplification hook switch detection dtmf detection on-hook transmission fsk generation (caller id) polarity reversal linear mode support (16-bit uncompressed voice data) iom-2 and pcm/c interface integrated test and diagnostic functions (itdf) line echo cancellation (lec) universal tone detection (utd) three-party conferencing message waiting lamp support slic slic iom ? -2 pcm c
p-mqfp-64-1,-2 p-tqfp-64-1 p-dso-20-5 p-vqfn-48-4 p-dso-36-12, -10 p-dso-36-15 dual channel subscriber line interface concept duslic peb 3264 peb 3265 peb 4264/-2 peb 4364 peb 4265/-2 peb 4365 peb 4266 preliminary data sheet 23 2003-07-11 type package peb 3264 p-mqfp-64-1 or p-tqfp-64-1 peb 3265 p-mqfp-64-1 or p-tqfp-64-1 peb 4264/-2 p-dso-20-5 or p-vqfn-48-4 peb 4364 p-dso-36-15 peb 4265/-2 p-dso-20-5 or p-vqfn-48-4 peb 4365 p-dso-36-15 peb 4266 p-dso-20-5 or p-vqfn-48-4 1.1 features fully programmable dual-channel codec programmable ac and dc characteristics integrated test and dia gnostic functions (itdf) programmable integrated ringing : balanced (85 vrms) and/or unbalanced (50 vrms) programmable teletax (ttx) generation programmable battery feed ing with capability for driving longer loops ground start/loop start signaling supported polarity reversal (hard or soft) on-hook transmission integrated dtmf generator integrated dtmf decoder integrated caller id generator (fsk or dtmf) universal tone detect ion (utd) - fax/modem detection integrated line echo cancellation (lec) up to 8 ms optimized filter struct ure for modem transmission three-party conferencing (in pcm/ c mode) message waiting lamp support (pbx) power optimized architecture power management cap ability (integrated battery switches)
duslic overview preliminary data sheet 24 ds3, 2003-07-11 8 khz and 16 khz pcm transmission iom-2 or pcm/c interface selectable g.711 a-law / -law companding specifications: itu-t g.712, q.552, lssgr, tr57 1.2 typical applications duslic offers an op timized solution for various applications. the following main applications can be highlighted: access networks ? central office (co) ? next-generation digital subscriber line access module (ng-dslam) ? digital loop carrier (dlc) ? wireless local loop (wll) ? fiber in the loop (fitl) ? digital added main line (daml) / pcm-x ? multi-dwelling / multi-tennant units (mdu / mtu) customer premises equipment ? private branch exchange (pbx) ? integrated access device (iad) ? voice over packet (vod sl, voip, voatm, etc.) ? isdn intelligent network termination (int) ? isdn terminal adapter (ta) ? cable modem ?xdsl nt ? router
duslic overview preliminary data sheet 25 ds3, 2003-07-11 1.3 logic symbols figure 2 logic symbol : slicofi-2/-2s ita itb itaca itacb ila ilb vcmita vcmitb dcpa dcpb dcna dcnb cdcpa cdcna cdcpb cdcnb vcm vcms acpa acpb acna acnb c1a c1b c2a c2b io1a io2a io3a io4a io1b io2b io3b io4b peb 3265 peb 3264 pcm/iom-2 fsc dcl/pclk dd/drb du/dout ts0/din ts1/dclk ts2/cs int mclk sel24/dra dxa dxb tca tcb rsync reset test cref selclk vdda vddb gnda gndb vddr gndr vddd gndd vddpll gndpll power supply logic control iom-2 interface c-interface pcm interface line current dc loop ac loop i/o feeding ezm14096
duslic overview preliminary data sheet 26 ds3, 2003-07-11 figure 3 logic symbol: slic-s /slic-s2 (v1.1, v1.2), slic-e/slic-e2 (v1.1) figure 4 logic symbol: sl ic-e/slic-e2 (v1.2) tip ring vdd agnd vhr bgnd vbatl vbath vcms cext it il acp acn dcp dcn c1 c2 peb 4264 peb 4264-2 peb 4265 peb 4265-2 tip/ring interface power supply logic control ac & dc feeding line current ezm14094 tip ring vdd agnd vhr bgnd vbatl vbath vcms cext it il acp acn dcp dcn c1 c2 peb 4265/-2 tip/ring interface power supply logic control ac & dc input voltage scaled line current outputs c3 ezm14094_12
duslic overview preliminary data sheet 27 ds3, 2003-07-11 figure 5 logic symbol: slic-p tip ring vcms cext it il acp acn dcp dcn c1 c2 c3 peb 4266 tip/ring interface logic control ac & dc feeding line current vdd agnd bgnd vbatl vbath vbatr power supply ezm14095
duslic overview preliminary data sheet 28 ds3, 2003-07-11 figure 6 logic symbol: tslic-s/tslic-e ezm14094tt peb 4364 peb 4365 vdda agnda vhra bgnda vbath power supply channel a vbatla tipa ringa tip/ring interface channel a ita ila line current channel a acpa acna dcpa dcna ac & dc feeding channel a c1a c2a logic control channel a vcmsa cexta vddb agndb vhrb bgndb vbath power supply channel b vbatlb tipb ringb tip/ring interface channel b itb ilb line current channel b acpb acnb dcpb dcnb ac & dc feeding channel b c1b c2b logic control channel b vcmsb cextb channel a channel b
duslic functional description preliminary data sheet 29 ds3, 2003-07-11 2 functional description 2.1 functional overview 2.1.1 basic functions of all duslic chip sets the functions described in th is section are integrated into all duslic chip sets (see figure 7 for duslic-s/-s2 and figure 8 for duslic-e/-e2/-p). all borscht functions are integrated: battery feed overvoltage protection (implemented by the robust high-voltage sl ic technology and additional circuitry) ringing 1) signaling (supervision) coding hybrid for 2/4-wire conversion testing an important feature of the duslic design is the fact th at all the slic and codec functions are programmable via the iom-2 or pcm/c interface of the dual-channel slicofi-2x device: dc (battery) feed characteristics ac impedance matching transmit gain receive gain hybrid balance frequency response in trans mit and receive direction ring frequency and amplitude 1) hook thresholds ttx modes 2) dtmf/tone generator because signal processing within the slicofi-2x is completely digita l, it is possible to adapt to the requirements list ed above by simply updating the coeffici ents that control dsp processing of all data. this means, for example, that changing impedance matching or hybrid balance requires no hardware modi fications. a single hardware design is now capable of meet ing the requirements for different markets. the digital nature of the filters and gai n stages also assures high reliability, no drifts (over temperature or time), and minimal variations betwee n different lines. 1) for the duslic-s2 chip set, only external ringing is supported 2) not available with the duslic-s2 chip set
duslic functional description preliminary data sheet 30 ds3, 2003-07-11 the characteristics for the two voice channels within slicofi-2x can be programmed independently of each other. the duslic coefficients software (duslicos) is provided to automate calculation of c oefficients to match differen t requirements. duslicos also verifies the calculated coefficients. 2.1.2 additional functions of the duslic-e/-e2/-p chip sets the following line circuit functions are int egrated only in the duslic-e/-e2/-p chip sets (see figure 8 ): teletax metering for pulse metering, a 12/16 khz sinusoidal metering burst must be transmitted. the duslic chip set genera tes the metering signa l internally and has an integrated notch filter. dtmf duslic has an integrated dtmf generator comprising two tone generators and one dtmf decoder. the decoder is able to monitor the transmit or receiv e path for valid tone pairs and outputs the corr esponding digital code fo r each dtmf tone pair. caller id frequency shift keying (fsk) modulator duslic has an integrated fs k modulator capable of sending caller id information. the caller id modulator complies with all requirements of it u-t recommendation v.23 and bell 202 (caller id can also be done using dtmf generators). line echo cancellation (lec) duslic contains an adaptive li ne echo cancellation unit for the cancellation of near end echoes (up to 8 ms cancel able echo delay time). universal tone detection (utd) duslic has an integrated univ ersal tone detection unit to detect special tones in the receive or transmit path (e.g. fax or modem tones).
duslic functional description preliminary data sheet 31 ds3, 2003-07-11 figure 7 line circuit functio ns in the duslic-s/-s2 figure 8 line circui t functions in the duslic-e/-e2/-p ezm22020 battery switch control logic tip ring current sensor & offhook detection gain slic-s/-s2 battery switch control logic tip ring current sensor & offhook detection gain adc dac hardware filters programmable filters and gain a-law or -law pcm / iom-2 interface adc dac hardware filters programmable filters and gain a-law or -law prefilter postfilter prefilter postfilter controller pcm interface iom-2 interface serial c interface slicofi-2s channel a channel b slic-s/-s2 interface control both slicofi-2s channels one slicofi-2s channel ringing ttx metering supervision digital signal processing (dsp) compander dcctl slic-s/-s2 ezm22007 battery switch control logic tip ring current sensor & offhook detection gain slic-e/-e2/-p battery switch control logic tip ring current sensor & offhook detection gain adc dac hardware filters programmable filters and gain a-law or -law pcm / iom-2 interface adc dac hardware filters programmable filters and gain a-law or -law prefilter postfilter prefilter postfilter controller pcm interface iom-2 interface serial c interface slicofi-2 channel a channel b slic-e/-e2/-p interface control both slicofi-2 channels one slicofi-2 channel ringing level metering ttx metering cid generation dtmf supervision digital signal processing (dsp) compander dcctl lec slic-e/-e2/-p utd
duslic functional description preliminary data sheet 32 ds3, 2003-07-11 2.2 block diagram slicofi-2/-2s figure 9 shows the internal block structure of all available slicofi-2x codec versions. the enhanced digital signal processor (edsp) provid ing the add-on functions 1) is only integrated in the slicof i-2 (peb 3265) device. figure 9 block diagram: slic ofi-2/-2s (peb 3265, peb 3264) 1) the add-on functions are dtmf detection, caller id ge neration, message waiting lamp support, three-party conferencing, universal tone detection (utd), li ne echo cancellation (lec), and sleep mode. ezm22021 dbus gnda gndd gndr gndpll vdda vddd vddr vddpll cref pcm/iom-2 reset super- vision prefi pofi adc dac + ila ita itaca vcmita acna acpa dcna dcpa cdcna cdcpa c1a c2a hw-fi hw-fi ima dsp cram contr c pcm iom-2 compand ilb itb itacb vcmitb acnb acpb dcnb dcpb c1b c2b cdcnb cdcpb pcm / c interface channel a hv interf. super- vision prefi pofi adc dac + hw-fi hw-fi ima channel b hv interf. edsp io1a io2a io3a io4a io1b io2b io3b io4b vcm vcms peb 3265 / peb 3264 peb 3265 only iom-2 interface or
duslic functional description preliminary data sheet 33 ds3, 2003-07-11 2.3 dc feeding dc feeding with the duslic is fully programmable as shown in table 4 on page 38 . figure 10 shows the signal paths for dc feeding between t he slic and the slicofi-2x : figure 10 signal paths ? dc feeding acp dcpb dcnb dcp dcn slic channel a slicofi-2x pcm out (data upstream) pcm in (data downstream) dcpa it il itaca ila ita vcm vcmita dcna dcp dcn slic channel b it il itacb ilb itb vcm vcmitb ring tip ring tip acpb acnb acn acpa acna acp acn pcm or iom-2 interface r ilb r it1b r it2b c itacb r ila r it1a r it2a transmit path receive path c vcmita c vcmitb transmit receive c itaca ezm140374
duslic functional description preliminary data sheet 34 ds3, 2003-07-11 2.3.1 dc characteristic feeding zones the duslic dc feeding charac teristic has three different zones: the constant current zone, the resistive zone, and the constant voltage zone. a voltage reserve v res (see chapter 2.3.7 ) can be selected to avoi d clipping the hi gh level ac signals (such as ttx) and to take into account the voltage drop of the slic. the dc feeding characteristic is shown in figure 11 . figure 11 dc feeding characteristic this simplified diagram shows the constant current zone as an ideal current source with an infinite internal resistance, while the co nstant voltage zone is shown as an ideal voltage source with an internal resistance of 0 ? . for the specificat ion of the internal resistances, see chapter 2.3.5 . ezm14017 i tip/ring i 0 constant voltage zone necessary voltage reserve v res |v bat | v tip/ring resistive zone constant current zone
duslic functional description preliminary data sheet 35 ds3, 2003-07-11 2.3.2 constant current zone in the off-hook state, the f eed current must usually be kept at a c onstant value independent of load (see figure 12 ). the slic senses the dc current and supplies this information to the slicofi-2x via the it pin (input pi n for dc control). the slicofi-2x compares the actual current with the prog rammed value and adjusts the slic drivers as necessary. i tip/ring in the constant curre nt zone is programmable from 0 to 32 ma or 0 to 50 ma depending on the partic ular slic version in use. figure 12 constant current zone depending on the load, the operating point is determined by the voltage v tip/ring between the tip and ring pins. the operating point is calculated from: v tip/ring = r load i tip/ring where r load = r pre + r line + r phone,off-hook r pre = r prot + r stab . the lower the load resistance r load , the lower the voltage between the tip and ring pins. a typical value for the programmable fe eding resistance in the constant current zone is about r i =10k ? (see table 4 ). ezm14016 i tip/ring i 0 v res |v bat | v tip/ring r load r k12 r i
duslic functional description preliminary data sheet 36 ds3, 2003-07-11 2.3.3 resistive zone the programmable resistive zone r k12 of the duslic provides extra flexibility over a wide range of applications. th e resistive zone is used fo r very long li nes where the battery is incapable of feeding a constant current into the line. the operating point in this case crosses from the consta nt current zone for low and medium impedance lo ops to the resistive zone fo r high impedance loops (see figure 13 ). the resistance of the zone r k12 is programmable from r v to 1000 ? . figure 13 resistive zone ezm14035 i tip/ring i 0 v res |v bat | v tip/ring r load r k12 r i
duslic functional description preliminary data sheet 37 ds3, 2003-07-11 2.3.4 constant voltage zone the constant voltage zone (see figure 14 ) is used in some applications to supply a constant voltage to th e line. in this case, v tip/ring = v lim is constant and the current depends on the load betwee n the tip and ring pin. v lim is set by the duslicos software. in the constant voltage zo ne, the external resistors r pre = r prot + r stab necessary for stability and protection define the resistance r v seen at the ring a nd tip wires of the application. the programmable range of the parameters r i , i 0 , i k1 , v k1 , r k12 and v lim is given in table 4 . figure 14 constant voltage zone ezm14036 i tip/ring i 0 v res |v bat | v tip/ring r load r k12 v lim
duslic functional description preliminary data sheet 38 ds3, 2003-07-11 2.3.5 programmable voltage and curre nt range: dc characteristics the dc characteristics and all symbols are shown in figure 15 . figure 15 dc characteristics table 4 dc characteristics symbol programmable range condition r i 1.8 k ? ?40k ? ? i 0 0 ? 32 ma only for duslic -s, duslic-e, duslic-p 0 ? 50 ma only for duslic-s2, duslic-e2 i k1 0 ? 32 ma only for duslic -s, duslic-e, duslic-p 0 ? 50 ma only for duslic-s2, duslic-e2 v k1 0?50v ? v k1 < v lim ? i k1 r k12 only ( v k1 , i k1 ) v k1 < v lim ? i k1 r v v k1 > v lim ? i k1 r k12 ( v k1 , i k1 ) and ( v k2 , i k2 ) r k12 r v ?1000 ? ? v lim 0?72v ? v lim > v k1 + i k1 r k12 only ( v k1 , i k1 ) i tip/ring i 0 v lim v tip/ring v k2 v k1 i k1 i k2 r i r k12 r v = r pre = r prot + r stab 1 2 ezm22009
duslic functional description preliminary data sheet 39 ds3, 2003-07-11 2.3.6 slic power dissipation the major portion of the power dissipation in the slic can be estimated by the power dissipation in the out put stages. the powe r dissipation can be calculated from: p slic ( v bat ? v tip/ring ) i tip/ring figure 16 power dissipation for further information, see chapter 3.7.2 on page 91 . ezm14021 i tip/ring i 0 |v bat | v tip/ring slic output stage power dissipation constant current zone slic output stage power dissipation constant voltage zone
duslic functional description preliminary data sheet 40 ds3, 2003-07-11 2.3.7 necessary voltage reserve to avoid clipping ac speech si gnals as well as ac meteri ng pulses, a voltage reserve v res (see figure 11 ) must be provided. v res =| v bat |? v lim (see page 37 ) | v bat | is the selected battery voltage, which can be either v bath , v batl , or | v hr ? v bath | for the slic-s/-s2/-e/-e2, depending on the mode. similarly, it can be v bath , v batl , or v batr for the slic-p, d epending on the mode. v res consists of: voltage reserve of the slic output buffer s: this voltage drop depends on the output current through the tip and ri ng pins. for a standard ou tput current of 25 ma, this voltage reserve is a few volts. voltage reserve for ac s peech signals: max. signal amplitude (example 2 v) voltage reserve for ac metering pulses: the ttx signal amplitude v ttx depends on local specifications and varies from 0.1 v rms to several vrms at a load of 200 ? . to obtain v ttx = 2 vrms at a load of 200 ? and r pre =50 ? ( r pre = r prot + r stab ), 3 vrms = 4.24 vpeak are needed at the slic output. therefore, a v res value of 10.24 v must be selected (= 4 v (slic drop for peak current of dc and speech and ttx) + 2 v (ac speech signals) + 4.24 v (ttx-signal)). figure 17 ttx voltage reserve schematic r pre slic r pre 200 ? v ttx ezm14032
duslic functional description preliminary data sheet 41 ds3, 2003-07-11 2.3.8 extended battery feeding if the battery voltage is not su fficient to supply the minimu m required current through the line even in the resistive zone, the auxili ary positive battery voltage can be used to expand the voltage swing between tip and ring . with this extended supply voltage ? v hr (duslic-s/-s2/e/-e2) or v batr (duslic-p) ? it is possibl e to supply the constant current for long lines. figure 18 shows the dc feedi ng impedances r max,acth in acth mode and r max,actr in actr mode (for more in formation about t he acth and actr modes, see chapter 3.1 ). figure 18 dc feeding charac teristics (acth, actr) the extended feeding characteristic is determi ned by the feeding characteristic in normal mode (acth) and an add itional gain factor k b (duslicos dc control parameter 1/4: additional gain in active ring): v lim,actr = v lim k b v k1,actr = v k1 k b + r v i k1 (k b ? 1) v k1 k b r k12,actr = k b ( r k12 ? r v ) + r v r k12 k b r i,actr = r i k b /2 i k2,actr = i k2 k b ( r k12 ? r v )/(k b r k12 ? r v ) v k2,actr = v lim,actr ? i k2,actr r v |v hr ? v bath | 1) |v bath | v tip/ring r max i k1 i tip/ring acth normal mode actr extended battery feeding mode r max, actr v k1, actr v k1 r k12, actr r k12 |v batr | 2) 1) duslic-s/-s2/-e/-e2, 2) duslic-p v lim v lim, actr ezm23019
duslic functional description preliminary data sheet 42 ds3, 2003-07-11 2.4 ac transmission characteristics slicofi-2x uses either an iom-2 or a pcm digi tal interface. in receive direction, slicofi-2x converts pcm data from the network and outputs a differential analog signal (acp and acn) to the slic that amplifies the signal and applies it to the subscriber line. in transmit direction, the transversal (it) an d longitudinal (il) cu rrents on the line are sensed by the slic and fed to the slicofi-2x . a capacitor separa tes the transversal line current into dc (it) and ac (itac) components. because itac is the sensed transversal (also called metall ic) current on the line, it includes both th e receive and transmit components. slicofi-2x separates the receive and transmit components digitally, via a transhybrid circuit. figure 19 shows the signal path s for ac transmission between the slics and slicofi-2x : figure 19 signal paths ? ac transmission the signal flow within the slicofi-2x for one voice channel is shown in schematic circuitry of figure 20 . with the exception of a few analog filter functions, signal processing is performed digitally in the slicofi-2x codec . acp dcpb dcnb dcp dcn slic channel a slicofi-2x dcpa it il itaca ila ita vcm vcmita dcna dcp dcn slic channel b it il itacb ilb itb vcm vcmitb ring tip ring tip acpb acnb acn acpa acna acp acn pcm or iom-2 interface r ilb r it1b r it2b c itacb r ila r it1a r it2a transmit path receive path c vcmita c vcmitb pcm out (data upstream) pcm in (data downstream) transmit receive c itaca ezm140373
duslic functional description preliminary data sheet 43 ds3, 2003-07-11 figure 20 signal flow in voice channel (a) 2.4.1 transmit path the current sense signal (itac) is converted to a voltage by an ex ternal resistor. this voltage is first filtered by an ant i-aliasing filter (pre -filter) that stops pr oducing noise in the voice band from signals near the a/d sampli ng frequency. a/d conversion is done by a 1-bit sigma-delta converter. the digital signal is down-sampled further and routed through programmable gain and fi lter stages. the coefficien ts for the filter and gain stages can be programmed to meet specific requirements. the processed digital signal goes through a compander (cmp) that co nverts the voice data into a-law or -law codes. a time slot assi gnment unit outputs t he voice data to the pr ogrammed time slot. slicofi-2x can also operate in 16-bit linear mo de for processing uncompressed voice data. in this case, tw o time slots are used for one voice channel. 2.4.2 receive path the digital input signal is received via th e iom-2 or pcm interface. expansion (exp), pcm low-pass filtering, freq uency response correction, and gain correction are performed by the dsp. the di gital data stream is up-sampled and converted to a corresponding analog si gnal. after smoothing by post-filters in the slicofi-2x , the ac signal is fed to the slic, wh ere it is superimposed on the dc signal. the dc signal has been processed in a separat e dc path. a ttx signal, generated digitally within slicofi-2x can also be added. ezm14026 pre- filter post- filter + teletax generator itac acp acn + amplify receive frequency response receive d/a ttx filter a/d amplify transmit + frequency response transmit cmp impedance matching transhybrid filter exp pcm out pcm in channel a channel b tg 1 tg 2 impedance matching slicofi-2x + cid generation dtmf detection transmit receive
duslic functional description preliminary data sheet 44 ds3, 2003-07-11 2.4.3 matching the slic outputs the voice si gnal to the line (receive dire ction) and also senses the voice signal coming from th e subscriber. the ac impedance of the slic and the load impedance need to be matched to maximi ze power transfer and minimize two-wire return loss. the two-wire re turn loss is a measure of t he impedance matching between a transmission line and the ac terminatio n of duslic. impedance matching is don e digitally within the slicofi-2x by three integrated impedance matching feedb ack loops. the loops feed the transmit signal back to the receive signal simulati ng the programmed impedanc e through the slic. when calculating the feedback filter coefficients, the external resistors between the protection circuit and the slic ( r pre = r prot + r stab , see figure 92 , page 357 ) must be taken into account. the impedance can be programmed to any ap propriate real and complex values shown in th e nyquist diagram figure 21 . this means that the device can be adapted to requ irements anywhere in the world wi thout requiring the hardware changes that are necessary with co nventional linecard designs. figure 21 nyquist diagram 0 -200 -400 -600 200 400 600 800 1000 1200 1400 re z l im z l possible values for line impedance ezm22019
duslic functional description preliminary data sheet 45 ds3, 2003-07-11 2.5 ringing because of the 170 v technolog y used for the slic, a ringin g voltage of up to 85 vrms sinusoidal or up to 100 vrm s trapezoidal can be generated on-chip without the need for an external ringing generator (this is with 20 v offset. higher ring amplitudes are possible if lower dc offs et voltage is required.) the slicofi-2x generates a sinusoidal ringing signa l that causes less noise and cross- talk in neighboring lines than a trapezoidal ringing si gnal. the ring ing frequency is programmable from 3 hz to 300 hz. slic-e/-e2, slic-s/-s2 and slic-p s upport different ringing methods (see chapter 2.5.3 ). 2.5.1 ringer load a typical ringer load can be th ought of as a resistor in se ries with a capacitor. ringer loads are usually described as a ringer equivalence number (ren) value. ren is used to describe the on-hook imp edance of the terminal equi pment and is actually a dimensionless ratio that refl ects a certain load. ren defi nitions vary from country to country. a commonly used ren is described in fcc part 68 that defines a single ren as either 5 k ? , 7 k ?, or 8 k ? of ac impedance at 20 hz. th e impedance of an n-multiple ren is equivalent to parallel connection of n single rens. in this manual, all references to ren assume the 7 k ? model. for example, a 1 ren and 5 ren load, ty pically used in t he usa, would be: figure 22 typical ringer loads of 1 and 5 ren used in usa 2.5.2 ring trip after the subscriber has gone off-hook, the ringing signal must be removed within a specified time, and powe r must start feeding to the subscriber's phone. there are two ring trip methods: dc ring trip detection and ac ring trip detection. dc ring trip detection most applications that utilize the duslic chip set use dc ri ng trip detection. by applying a dc offset together with the ringing signal, a tran sversal dc loop current starts to flow when the subscriber goes off- hook. this dc current is se nsed by the slic and in this way is used as an off-hook criterion. th e slic supplies this information to the slicofi-2x at the it pin. the slicofi-2x continuously integrates the sensed line 1 ren 5 ren 8 f 40 f 1386 ? 6930 ? ezm14024
duslic functional description preliminary data sheet 46 ds3, 2003-07-11 current i trans over one ringer period. this causes the integration result to represent the dc component of the ring current. if the dc current exceeds the programmed ring trip threshold, slicofi-2x generates an interrupt. ring trip is reliably detected and reported within two ring signal periods. the ringing signal is switch ed off automatically at zero crossing by the slicofi-2x . the threshold for the ring trip dc current is set internally in the slicofi-2x and programmed via the digital interface. the dc offset for ring trip detection can be generated by the duslic chip set an d the internal ring trip function can be used even if an external ringing generator is used. ac ring trip detection for short lines (< 1 k ? loop length) and for low-power applications , the dc offset can be avoided to reduce the battery voltage for a given ring amplit ude. ring trip detection is done by rectifying the ring current i trans , integrating it over one ringer period and comparing it to a programmable ac ring trip threshold. if the ring current exceeds the programmed threshold, the hook bit in register intreg1 is set accordingly. most applications that utilize the duslic chip set use the dc ring trip detection, which is more reliable than ac ring trip detection. 2.5.3 ringing methods there are two methods of ringing: balanced ringing (bridged ringing) unbalanced ringing (divided ringing) internal balanced ringing generally offers more benef its compared to unbalanced ringing: balanced ringing produces mu ch less longitudinal voltage, which results in a lower amount of noise coupled into adjac ent cable pairs (e.g. adsl lines). by using a differential ringi ng signal, lower supply voltages become possible the phone itself cannot distin guish between balanced and unbalanced ringing. where unbalanced ringing is still used, it is often simply an historical leftover. for a comparison between balanced and unbalanced ringing, see also ansi document t1.401-1993. additionally, integrated ringi ng with the duslic offers the following advantages: internal ringing (no need for exte rnal ringing gene rator and relays) reduction of board space be cause of much higher inte gration and fewer external components programmable ringing amplitude, frequency, and ringing dc offs et without hardware changes programmable ring trip thresholds switching of the ringing si gnal at zero-crossing. with relays there is always some residual switching noise, whic h can cause interference on adjacent cable pairs (e.g. adsl).
duslic functional description preliminary data sheet 47 ds3, 2003-07-11 2.5.4 duslic ringing options application requiremen ts differ with regard to ringin g amplitudes, po wer requirements, loop length, and loads. the duslic options include three different slics to ensure the most appropriate ri nging methods (see table 5 ) for these applications: slic-s allows balanced ringi ng up to 45 vrms and is de dicated to short loop or pbx applications. table 5 ringing options with sl ic-s, slic-e/-e2 and slic-p slic version/ ringing facility, battery voltages slic-s peb 4264 slic-e/-e2 peb 4265 peb 4265-2 slic-p peb 4266 internal max. balanced ringing voltage in vrms [with 20 v dc used for ring trip detection] sinusoidal trapezoidal 45 vrms 53 vrms 85 vrms 100 vrms 85 vrms 100 vrms dc voltage for balanced ringing 1) 1) in most applications, 20 v dc are sufficient for reliable ri ng trip detection. a higher dc voltage will reduce the achievable maximum ringing voltage. for short loops, 10 v dc may be sufficient. programmable typ. 0 ? 50 v programmable typ. 0 ? 50 v programmable typ. 0 ? 50 v internal unbalanced ringing max. voltag e in vrms sinusoidal trapezoidal no no no no 50 vrms 58 vrms dc voltage for unbalanced ringing no no v batr /2 required slic supply voltages for maximum ringing amplitude (typically) v dd =5v 2) , v dd =3.3v 3) v bath = ?54 v, v hr =36v 2) 170 v technology 3) 90 v technology v dd =5v, v bath =?70v, v hr =80v v dd = 5 v or 3.3 v, v bath = ?48 v, v batr =?150v number of battery voltages for power saving 2 ( v batl & v bath ) 2 ( v batl & v bath ) 2 (when internal ringing is used) 3 (when external ringing is used)
duslic functional description preliminary data sheet 48 ds3, 2003-07-11 for slic-s2, only exter nal ringing is provided. slic-e/-e2 allows balanced ringing up to 85 vrms and can, therefore, be used in systems with higher loop impedance. the low-power slic-p is optimized for power -critical applications (such as intelligent isdn network termination). inte rnal ringing can be used up to 85 vrms balanced or 50 vrms unbalanced. for lowest power applications where ex ternal ringing is preferred, three different battery voltages ( v batr , v bath , v batl ) can be used to optimize the power consumption of the application. 1) slic-e/-e2 and slic-p differ in supply voltage configuration and the ring voltages at tip and ring v t and v r . external ringing is su pported by both slics. both internal and external ri nging are activated by switching the duslic to ringing mode by setting the cidd/ciop 2) bits m2, m1, m0 to 101 (see ?overview of all duslic operating modes? on page 74 ). external ringing support by duslic the following setti ngs must be made: enable the use of an external ring signal generator by se tting bit rext-en in register bcr2 to 1. a ttl compatible zero cros sing signal must be applie d to the rsync pin of the slicofi-2x (see figure 23 ). activate the ringing mode by setting the cidd/ciop bits m2, m1, m0 to 101. set the duslic internal ri ng frequency to a value accordin g a factor of approximately 0.75 of the external ring frequency. the ring relay is controll ed by the io1 pin (see figure 92 ). due to the high current drive capability of the io1 ou tput, no additional rela y driver is necessary. the relay is switched ei ther synchronously or asynchronously as follows: synchronous to the zero crossing of the external ringing frequency (bit asynch-r in regi ster xcr set to 0) a ring generator delay t ring,delay (see duslicos control parameters 2/4) can be programmed to consider the ring relay delay t ring-relay,delay as shown in figure 23 . asynchronous (bit asynch-r in regi ster xcr set to 1) the ring relay is switched im mediately with the ring command. 1) in this case, v batr is typically used for the on-hook state, while v bath and v batl are used for optimized feeding of different loop length s in the off-hook state. 2) cidd = data downstream command/indica tion channel byte (iom-2 interface) ciop = command/indication operation
duslic functional description preliminary data sheet 49 ds3, 2003-07-11 figure 23 external ringing ze ro crossing synchronization external ringing voltage t t t v rsync v io 1 t ring,delay t ring-relay,delay t v ring duslic_0015_zero_crossing
duslic functional description preliminary data sheet 50 ds3, 2003-07-11 2.5.5 internal balanced ringing via slics slic-e/-e2 and slic-p support in ternal balanced ringing up to v ring,rms = 85 vrms, while slic-s supports balanced ri nging up to v ring,rms = 45 vrms 1) . the ringing signal is gener ated digitally within the slicofi-2x . figure 24 balanced ri nging via slic-e/-e2, slic-s and slic-p in ringing mode, the dc feedi ng regulation loop is not ac tive. a programmable dc ring offset voltage is applied to th e line instead. during ring bursts, the ringing dc offset and the ringing signal are summed digitally within slicofi-2x in accordance with the programmed values. this signal is then conv erted to an analog sign al and is applied to the slic. the slic amplifies th e signal and supplie s the line with ri nging voltages up to 85 vrms. in balanced ringing mode, the sl ic uses an additio nal supply voltage v hr for slic-e/-e2/-s and v batr for slic-p. the tota l supply span is now v hr ? v bath for slic-e/-e2/-s and v batr for slic-p. the maximum ringing voltage that can be achieved is: for slic-e/-e2/-s: v ring,rms =( v hr ? v bath ? v drop,tr ? v dc,ring )/1.41 for slic-p: v ring,rms =( ? v batr ? v drop,tr ? v dc,ring )/1.41 where: v drop,tr = v drop,t + v drop,r 1) in this case v ring,rms = v tr,rms = v tr0,rms because of the low impedance of the slic output (< 1 ? ). v tr,rms is the open-circuit rms voltage measured directly at pi ns ring and tip at the sl ic output with ringer load. v tr0,rms is the rms voltage measured directly at pins ring and tip at the slic output without any ringer load. for calculation of the ringing voltage at th e ringer load, see the application note duslic voltage and power dissipation calculation and its accompanying ms excel sheet for calculation. ezm140315 v dc,ring v r v t v drop,t v drop,r v ring,pp = v tp - v rp v batr bgnd slic-e slic-e2 slic-s slic-p v bath v hr v tp v rp
duslic functional description preliminary data sheet 51 ds3, 2003-07-11 using the duslic chip set, ringing voltages up to 85 vrms sinusoidal can be applied, and trapezoidal ringing ca n be programmed as well. for a detailed application diagram of internal balanced ringing see figure 90 on page 353 . 2.5.6 internal unbalanced ringing with slic-p the internal unbalanced ring ing supported by slic-p ca n be used for ringing voltages up to 50 vrms. the slicofi-2 integrated ring ing generator is used and the ringing signal is applied to either the tip or ring line. ringing signal gener ation is the same as described above for balanced ri nging. as only one line is used for ringing, technology limits the ringing amplitude to about half t he value of balanced ri nging, to a maximum of 50 vrms. figure 25 unbalanced ringing signal figure 25 shows an example with th e ring line used for ringing and th e tip line fixed at ? v drop,t which is the drop in the ou tput buffer of the tip line of slic-p (typ. < 1 v). the ring line has a fi xed dc voltage of v batr /2 used for ring trip detection. the maximum ringing voltage is: v ring,rms =( ? v batr ? v drop,r,vbatr ? v drop,t )/2.82 when the called subscriber goes off-hook, a dc path is established from the ring to the tip line. the dc current is recognized by the slicofi-2 because it monitors the it pin. an interrupt indicates ring trip if the li ne current exceeds th e programmed threshold. the same hardware can be used for integr ated balanced or unb alanced ringing. the balanced and unbalanced modes are config ured by software. th e maximum achievable amplitudes depend on the values selected for v batr . v batr / 2 v t v r v ring,p v dc,ring v drop,r,vbatr v drop,r,bgnd v drop,t v drop,t v batr bgnd v ring = v r ezm140316
duslic functional description preliminary data sheet 52 ds3, 2003-07-11 in both balanced and unbalanced ringing modes, slicofi-2 auto matically applies and removes the ringing signal du ring zero-crossing. this reduces noise and cross-talk to adjacent lines. 2.5.7 external unbalanced ringing slicofi-2x supports external (balanced or unba lanced) ringing fo r higher ringing voltage requirements with al l slic versions. in this ca se, the integrated ring trip functionality of the duslic may be us ed. for a detailed application diagram of unbalanced ri nging, see figure 92 ( page 357 ) and figure 94 ( page 359 ). because high voltages are involv ed, an external relay should be used to switch the ring line off and to switch the ex ternal ringing signal together with a dc voltage to the line. the dc voltage must be applie d for the internal ring tr ip detection mechanism that operates for external ri nging in the same way as for internal ringing. the slicofi-2x must be set to the external ringing mode by the rext-en bit in register bcr2. a synchronization signal of the external ringer is applied to the slicofi-2x via the rsync pin. the external relay is switched on or off synchronousl y to this signal via the io1 pin of the slicofi-2x , according to the actual mode of the duslic. an interrupt is generated if the dc current exceeds the progra mmed ring trip threshold. 2.6 signaling (supervision) signaling in the subscriber loop is monitored internal ly by the duslic chip set. supervision is performed by sensing the longi tudinal and transversal line currents on the ring and tip wires. the scal ed values of these currents are generated in the slic and are fed to the slicofi-2x via the it and il pins. transversal line current: i trans =( i r + i t )/2 longitudinal line current: i long =( i r ? i t )/2 where i r , i t are the loop currents on the ring and tip wires. off-hook detection loop start signaling is the mo st common type of signaling. the subscriber loop is closed by the hook switch inside the subscriber equipment. in active mode, the resulting transversal loop current is sensed by the internal current sensor in the slic. the it pi n of the slic indicates the s ubscriber loop current to the slicofi-2x . external resistors ( r it1 , r it2, see figure 90 on page 353 ) convert the current information to a volt age on the ita (or itb) pin. the analog information is first converted to a digital value. it is then filtered and processed further which effectively supp resses line disturba nces. if the result exceeds a programmable threshold, an inte rrupt is generated to indicate off-hook detection.
duslic functional description preliminary data sheet 53 ds3, 2003-07-11 in sleep/power down mode (pdrx), a similar mechanism is used. in this mode, the internal current sensor of the slic is sw itched off to minimi ze power consumption. the loop current is therefore fed and sensed through 5 k ? resistors integrated within the slic. the information is made available on the it pin and is interpreted by the slicofi-2x . ? in sleep mode, the analog information is fe d to an analog comparator integrated within the slicofi-2x that directly in dicates off-hook. ? in power down mode, the slicofi-2x converts the analog in formation to a digital value. it is then filter ed and processed further to effectively suppress line disturbances. if the result exceeds a programmable th reshold, an interrupt is generated to indicate off-hook detection. in applications using ground start signaling, duslic can be set to the ground start mode. in this mode, the tip wire is switched to high impeda nce mode. ring gr ound detection is performed by the internal current sensor in the slic and is transferred to the slicofi-2x via the it pin. ground key detection the scaled longitudinal current information is transferred from the slic via the il pin and the external resistor r il to slicofi-2x . this voltage is compar ed with a fixed threshold value. for th e specified r il (1.6 k ? , see application circuit figure 90 , page 353 ) this threshold corresponds to 17 ma (positive an d negative). after fu rther post-processing, this information generates an interrupt (gndk bi t in the intreg1 re gister) and ground key detection is indicated. the polarity of the longitudi nal current is indicated by the gnkp bit in the intreg1 register. each change of th e gnkp bit generates an inte rrupt. both bits (gndk, gnkp) can be masked in the mask register. the post-processing is performed to gu arantee ground key detection, even if longitudinal ac currents with frequencies of 16 2 / 3 , 50 or 60 hz are superimposed. the time delay between triggering the ground key function and registering the ground key interrupt will be less than 40 ms in most cases ( f =50hz, 60hz). for longitudinal dc signal s, the blocking period can be programmed by the data upstream persistence counter end value (dup) in register ioctl3. dc signals with less duration will not be detected. the dup time is equivalent to the half of the cycle time for the lowest frequency for ac suppression (for values see register ioctl3 on page 166 ). in power down mode, the slic?s internal current sensors are sw itched off and ground key detection is disabled.
duslic functional description preliminary data sheet 54 ds3, 2003-07-11 2.7 metering one of two different meteri ng methods may be specified: metering by sinusoidal burst s of either 12 khz or 16 khz polarity reversal of tip and ring. 2.7.1 metering by 12/16 khz sinusoidal bursts to satisfy worldwide app lication requirements, slicofi-2/ -2s offers integrated metering injection of either 12 or 16 khz signals with programmabl e amplitudes. slicofi-2/-2s also has an integrated adaptive ttx notch filt er and can switch the ttx signal to the line in a smooth way. when switch ing the signal to the line, the switching noise is less than 1mv. figure 26 shows ttx bursts at certain points of the signal flow within slicofi-2/- 2s. figure 26 teletax injection and metering the integrated, adaptive ttx notch filter guarantees an attenuation of > 40 db. no external components for filter ing ttx bursts are required. ezm14027 slicofi-2/-2s a/d d/a d / a ttx adaptive filter ttx gen. im filter + slic-e/-e2 slic-s slic-p x1 - y receive path transmit path z l /2 z l /2 + +
duslic functional description preliminary data sheet 55 ds3, 2003-07-11 2.7.2 metering by polarity reversal slicofi-2/-2s also supports metering by polarity revers al by changing the actual polarity of the voltages on th e tip/ring lines. polarity revers al is activated by switching the revpol bit in register bc r1 to one or by switching to the ?active with metering? mode by the cidd or ciop command (see ?overview of all duslic operating modes? on page 74 ). 2.7.2.1 soft reversal some applications require a smooth polarity reversal (soft reve rsal), as shown in figure 27 . soft reversal helps prevent negative e ffects such as non-r equired ringing. soft reversal is deactivated by the soft-dis bit in register bcr2. figure 27 soft reversal (e xample for open loop) start: the soft ramp starts by setting th e revpol bit in register bcr1 to 1. the dc characteristic is switched off. sr-end1: at the soft reversal end one point, the dc characteri stic is switched on again. programmable by the duslic os software, such as ? u/8. sr-end2: at the soft reversal end tw o point, the soft ra mp is switched off. programmable by the duslicos software, such as 1/16 sr-end1. from start to sr-end2 the ready bit in re gister intreg2 is set to 0 (see register description in chapter 5.3.1.2 for further information). soft-dis = 1 immediate reversal is performed (hard reversal) soft-dis = 0 soft reversal is performed. tr ansition time (tim e from start to sr-end1, see figure 27 ) is programmable by cram coefficients; default value is 80 ms. 0 50 100 150 200 250 -25 -20 -15 -10 -5 0 5 10 15 20 25 t [ms] v tip/ring [v] sr-end1 ? u ? u/8 sr-end2 = 1/16*sr-end1 start ezm14038
duslic functional description preliminary data sheet 56 ds3, 2003-07-11 2.8 duslic enhanced signal processing capabilities the signal processing capabilities describ ed in this section are implemented by an enhanced digital signal proce ssor (edsp), with the exce ption of dtmf generation. each function can be indivi dually enabled or disabled for each duslic channel. therefore, power consumption can be reduced according to the needs of the application. for the mips requirements of th e different edsp algorithms see chapter 2.8.6 . figure 28 shows the ac signal path for dusl ic with the adcs and dacs, impedance matching loop, trans-hybrid filter, gain stages, and t he connection to the edsp. figure 28 duslic ac signal path figure 29 shows a close-up on the ed sp signal path shown in figure 28 identifying signal names a nd sop commands. figure 29 duslic edsp signal path edsp cmp exp dtmf lec ax1 hpx1 cid + ar1 hpr1 tg lpx frx lpr frr th ax2 hpx2 ar2 hpr2 im3 ttxa + dac dac adc im2 + + im1 + xout rin vin vout ttxg utd utd switch duslic_0005_acsignal_path cmp utdx dtmf utdr exp g lec g g ar1 lpr frr + + cid tg ax1 hpx1 lpx frx th lec-en utdx-sum utdx-src utdx-en dtmf-src utdr -sum utdr-en rin xout s lec,tin s lec,r s lec,tout s sum g g dtmf g lec-x0 g lec-xi g lec-ri s x s r lec-out lec-en dtmf-en duslic_0006_edspsignal_path switch position shown for control bit set to 0
duslic functional description preliminary data sheet 57 ds3, 2003-07-11 the enhanced signal processing ca pabilities are available on ly for the duslic-e/-e2/-p versions, with an except ion of dtmf generation. the dtmf generation is availa ble for all duslic versions. the functions of the edsp are configured a nd controlled by pop register settings (see chapter 5.2.3 ). 2.8.1 dtmf generation and detection dual tone multi-frequency (dtmf) is a signaling scheme using voice frequency tones to signal dialing information. a dtmf signal is the sum of two tones, one from a low group (697?941 hz) and one from a high group (1209?1633 hz), with each group containing four individual tones. this scheme allows si xteen unique combinations. ten of these codes represent the numbers from zero through nine on the telephone keypad, the remaining six codes (*, #, a, b, c, d) are reserved for special signaling. the buttons are arranged in a matrix , with the rows determining the low group tones, and the columns determining the high group tone for each button. in all slicofi-2x codec versions, the sixteen standard dtmf tone pairs can be generated independent ly in each channel via tw o integrated tone generators. alternatively, the frequency and amplitude of the tone ge nerators can be programmed individually via the digital inte rface. each tone ge nerator can be switc hed on and off. the generated dtmf tone signals m eet the frequency vari ation tolerances specified in the itu-t q.23 recommendation. both channels a and b of slicofi-2 1) have a powerful built-in dtmf decoder that will meet most nationa l requirements. the receiver algorit hm performance meets the quality criteria for central office/exch ange applications. it compli es with the requirements of itu-t q.24, bellcore gr-30-core (tr-nw t-000506), and deut sche telekom network (bapt 223 zv 5, approval specification of the federal office for post and telecommunications, ge rmany), among others. note: dtmf detection is only available for duslic-e/-e2/-p the performance of the algorithm can be adapted accord ing to the needs of the application via the digital in terface (detection level, tw ist, bandwidth, and center frequency of th e notch filter).
duslic functional description preliminary data sheet 58 ds3, 2003-07-11 table 6 shows the performance characterist ics of the dtmf decoder algorithm: table 6 performance characteristics of the dtmf decoder algorithm no. characteristic value notes 1 valid input signal detection level ?48 to 0 dbm0 programmable 2 input signal rejection le vel ?5 db of valid signal detection level ? 3 positive twist accept < 8 db programmable 4 negative twist acce pt < 8 db programmable 5 frequency deviation acce pt < (1.5% + 4 hz) and < 1.8% related to center frequency 6 frequency deviation reject > 3% related to center frequency 7 dtmf noise tolerance (could be the same as 14) ?12 db db referenced to lowest amplitude tone 8 minimum tone accept duration 40 ms ? 9 maximum tone reject duration 25 ms ? 10 signaling velocity 93 ms/digit ? 11 minimum inter-digit pause duration 40 ms ? 12 maximum tone drop-out duration 20 ms ? 13 interference rejection 30 hz to 480 hz for valid dtmf recognition level in frequency range 30 hz ? 480 hz level of dtmf frequency +22 db db referenced to lowest amplitude tone 14 gaussian noise influence signal level ?22 dbm0, snr = 23 db error rate better than 1 in 10000 ? 15 pulse noise influence impulse noise tape 201 according to bellcore tr-tsy-000762 error rate better than 14 in 10000 measured with dtmf level ?22 dbm0 impulse noise ?10 dbm0 and ?12 dbm0
duslic functional description preliminary data sheet 59 ds3, 2003-07-11 in the event of pauses < 20 ms: if the pause is followed by a tone pair with the same fr equencies as before, this is interpreted as drop-out. if the pause is followed by a tone pair with different frequenci es and if all other conditions are valid, this is in terpreted as two different numbers. dtmf decoders can be switched on or off individu ally to reduce po wer consumption. in normal operation, the decode r monitors the tip and ring wires via the itac pins (transmit path). alternatively, the decoder can also be switched in the receive path. on detection of a valid dtmf tone pair, slicofi-2 generat es an interrupt via the appropriate int pin and indicates a change of status. the dtmf code information is provided by a register that is read via the digital interface. the dtmf decoder also has e xcellent speech-rejection capa bilities and complies with bellcore tr-tsy-000763. the algorithm has been fully te sted with the speech sample sequences in the series-1 digit simula tion test tapes fo r dtmf decoders from bellcore. the characteri stics of dtmf detection can be controlled by pop registers 30h to 39 h . 2.8.2 caller id generation in duslic-e/-e2/-p a generator to send calling li ne identification (caller id, cid) is integrated in the duslic-e/-e2/-p chip set. call er id is a generic name fo r the service provided by telephone utilities that supply information such as the telephone number or the name of the calling party to the called subscriber at the start of a ca ll. in call waiting, the caller id service supplies information about a second in coming caller to a subscriber already busy with a phone call. in typical caller id systems, the coded calling number info rmation is sent from the central exchange to the called phone. this informa tion can be shown on a display on the subscriber telephone set. in this case, the caller id info rmation is usually displayed before the subscriber decides to answer the incomi ng call. if the line is connected to a computer, caller information c an be used to search in databases and additional services can be offered. there are two methods used for sending cid information de pending on the application and country-specific requirements: caller id generation usin g dtmf signaling (see chapter 2.8.1 ) caller id generation using fsk duslic-e/-e2/-p contains dtmf generation units and fsk generati on units that can be used for both channe ls simultaneously. the characteristics of the ca ller id generation circuitry can be controlled by pop registers 00 h , 43 h to 4a h .
duslic functional description preliminary data sheet 60 ds3, 2003-07-11 duslic-e/-e2/-p fsk generation different countries use different stan dards to send caller id information. the duslic-e/-e2/-p chip set is compatible with the widely used bellcore gr-30- core, british telecom (bt) sin227, si n242, and the uk c able communications association (cca) specification tw/p&e/3 12 standards. conti nuous phase binary frequency shift keying (fsk) modulation is used fo r coding that is compatible with bell 202 (see table 7 ) and itu-t v.23, the most comm on standards. the slicofi-2 can be easily adapted to these requirements by pr ogramming via the microcontroller interface. coefficient sets are prov ided for the most common standards. the caller id data of the callin g party can be transferred via the microcontroller interface into a slicofi-2 buffer regist er. the slicofi-2 will start sending the fsk signal when the cis-en bit is set and the cid-data buffer is filled up to cis-brs plus 1 byte. the data transfer into the buffe r register is handled by a slicofi- 2 interrupt signal . caller data is transferred from the buffer via the interface pi ns to the slic-e/-e2/- p and is fed to the tip and ring wires. the caller id data bytes from the cid-data buffer are sent with the least significant bit (lsb) first. duslic-e/-e2/-p offers two di fferent levels of framing: a basic low-level framing mode all the data necessary to implement the fsk data stream?i ncluding channel seizure, mark sequence, and framing fo r the data packet or checksum?must be configured by firmware. slic ofi-2 transmits the data st ream in the same order in which the data is writte n to the buffer register. a high-level framing mode the number of channel se izure and mark bits ca n be programmed and are automatically sent by the duslic-e/-e2/-p. only the data packet information must be written into the cid buffer . start and stop bits are aut omatically inserted by the slicofi-2. the example below shows t he signaling of a cid on-h ook data transmission in accordance with be llcore specifications. the caller id information applied on tip and ring is sent during the period betw een the first and second ring burst. table 7 fsk modulation characteristics characteristic itu-t v.23 bell 202 mark (logic 1) 1300 3 hz 1200 3 hz space (logic 0) 2100 3 hz 2200 3 hz modulation fsk transmission rate 1200 6 baud data format serial binary asynchronous
duslic functional description preliminary data sheet 61 ds3, 2003-07-11 figure 30 bellcore on-hook caller id physical layer transmission note: as a cid transmission is a n on-hook transmission the duslic has to be programmed to actice mode. 2.8.2.1 caller id buffer handling of slicofi-2 this section describes the handling of the caller id bu ffer and the corresponding handshake bits in th e interrupt registers. programming sequence in order to send caller id information over the telephone line, the following sequence should be programmed between th e first and the second ring burst. the initialization part of the coefficients in the po p registers 43h to 4ah must be done prior to that sequence. 1. enable the extended feature ds p in register xcr (edsp-en = 1) 2. enable the caller id sender feat ure in register bcr5 (cis-en = 1) 3. wait for an interrupt. 4. read out all 4 interru pt registers to serve the interr upt and check the cis-req bit. bellcore on-hook caller id physical layer transmission first ring burst channel seizure mark data packet second ring burst abc d efg more parameter messages more parameter bytes message type message length 1 parameter type parameter length parameter byte checksum parameter message parameter header parameter body message header message body message 1 message length equals the number of bytes to follow in the message body, excluding the checksum. a: 0.2 - 3 second ring burst b: 0.5 - 1.5 seconds between first ring burst and start of data transmission c: 300 alternating mark and space bits d: 180 mark bits c + d + e = 2.9 to 3.7 seconds f: 200ms g: 1.8 - 3 second ring burst ezm14014
duslic functional description preliminary data sheet 62 ds3, 2003-07-11 5. if this bit is set, write at least brs + 2 bytes (see pop re gister cis-brs) of caller id data but not more than 48 by tes to the caller id sender buffer register cis-dat. 6. wait for the next interrupt and check again the cis-req bit. 7. if this bit is set, send t he next data to the caller id-dat a buffer but not more than (48 ? brs) bytes. cis-req bit gets reset to 0, if the data buffe r is filled aga in above the caller id sender buffer request size (brs). 8. repeat steps 6 and 7 as long as there is data to be sent. 9. immediately after sending the last caller id data bit to t he caller id sender buffer, set the bit cis-auto to 1 and subs equently, after a time delay of at least 500 s, the bit cis-en to 0. after processing the last bit, the caller id sender will stop automatically and reset the cis-act bit in register intreg4 to 0. no more cis interrupts will be generated until the caller id sender is en abled again (interrupt bits: cis-bof, cis- buf and cis-req). the end of the cid transmission can also be controlled by not setting cis-auto and leaving cis-en at 1. if the ca ller id buffer becomes empty, an interrupt is generated to indicate buffer underflow (cis-b uf). if cis-buf is set, reset cis-en to 0 with at least 1 ms delay, in order to allow to send the la st bit of caller id data. in case of errors in the han dling of the cid data buffer, cis-buf (buffer underflow) and cis-bof (buffer overflow) indi cate these errors. cid transm ission should be stopped in any of these cases as unpr edictable results may occur. note: cid data will be sent out with the lsb first if cis-frm is set to 1: seiz ure and mark bits are generat ed automatically (according to the settings of cis-seiz-h/l and cis-mark-h/l ) as well as start and stop bits for every byte.
duslic functional description preliminary data sheet 63 ds3, 2003-07-11 2.8.3 line echo cancellation in duslic-e/-e2/-p the duslic-e/-e2/-p contains an adaptive line echo cancellation (lec) unit for the cancellation of near end echoes. with th e adaptive balancing of the lec unit, the transhybrid loss can be improved up to a value of approximately 50 db. the maximum echo cancellation time selectable is 8 ms. the line echo cancellation unit is especially useful in combination with the dtmf detection unit. in critic al situations the performance of the dtmf detectio n can be improved. if a line echo cancellation le ngth (lec length) of 8 ms is used, please take care about the mips requirement s described in chapter 2.8.6 . the duslic-e/-e2/-p line echo canceller is compatible with applicable itu-t g.165 and g.168 standards. an echo cancellation de lay time of up to 8 ms can be programmed. the lec unit basically consists of an finite impulse resp onse (fir) filter, a shadow fir filter, and a coefficient ad aptation mechanism between th ese two filters as shown in figure 31 . figure 31 line echo cancella tion unit block diagram the adaptation process is contro lled by the three parameters pow lecr (power detection level receive), deltap lec (delta power) and delt aq (delta quality) ( ?pop command? on page 207 ). adaptation takes place only if bo th of the followi ng conditions hold: 1. s lec,r >pow lecr 2. s lec,r ?s lec,tin >deltap lec with the first condition, adapt ation to small signals can be avoided. the seco nd condition avoids adaptation during doubl e talk. the pa rameter deltap lec represents the echo loss shadow fir filter copy coeff. fir filter adapt coeff. s lec,r s lec, tin s lec, tout duslic_0004_lecunit
duslic functional description preliminary data sheet 64 ds3, 2003-07-11 provided by external circuitry. if the adaptation of the shadow filter is performed better than the adaptation of the actu al filter by a value of mo re than deltaq, then the shadow filter coefficients will be copied to the actual filter. at the start of an adaptation process, the coefficients of the lec unit can be reset to de fault initial values or can be set to the old coefficient values. the coef ficients may also be frozen. 2.8.4 non linear processor (nlp) in duslic-e/-e2/-p in slicofi-2 version 1.5 a non linear proc essor (nlp) in additi on or as an option to the existing line echo cancel ler (lec) is implemented. plea se note that the nlp is not available with slicofi-2 version 1.5. the principle of the nlp is ba sed on a limitation of the input signal. this means, that all samples which are below a limit (in the case of a negative samp le above the negative limit), can pass the nlp without any modification. all sample s which are above the limit (in the case of a negative sample below the negative limit), wi ll be set to this limit (or negative limit). the value for the limit is the estimated backgr ound noise. the advantage of the limitation is, that the background noise can pass the nlp unchanged. therefore the far end talker can not hear the nlp. the decision when the nlp should be activate d, is based on the estimated residual echo after the lec. if the signal af ter the lec is highe r than the estimated residual echo, the nlp is bypassed. when both the transmit and receive speech detectors are detecting speech (double talk), the nlp is also bypassed. an overhang counter ensures, that the end of the speech signal can pass the nlp unchanged. if end of speech is detected, the overhang counter starts counting from a predefined start val ue down to zero. this ti me ensures that silent parts at the end of t he speech are not ignored. important coefficients: ? bn-lev-x, bn-lev-r, bn-max and bn-adj for the background noise estimation ? re-est-erll for the nlp be havior in the simple mode ? sd-lev-r, sd-lev-x and sd-lev-r e for the speech detection ? ct-lev-re for early double ta lk and near e nd speech detection for all other coefficients the default values (see table 5.2.3.4 ) should be chosen. lec and nlp implementation the nlp is integrated in the lec unit. that means when the lec and nlp are active, the output signal of the le c is influenced by the nlp. if the dtmf receiver and/or the universal tone detection (u td) unit are active, the input signal for both is the le c and the nlp output signal 1) . usually this is no problem, as the 1) for the utd this is only valid when the sum signal of receive and transmit is fed to the utd (see figure 29 ).
duslic functional description preliminary data sheet 65 ds3, 2003-07-11 nlp bypasses local dtmf signals, but it woul d be a good strategy to only enable the nlp after the call has been completely es tablished (far end talker connected). 2.8.5 universal tone detect ion in duslic-e/-e2/-p each channel of the duslic-e/-e2/-p has tw o universal tone detection (utd) units that can be used to detect specia l tones in the receive and tran smit paths, especially fax or modem tones (for example, se e the modem startup sequence described in the itu-t v.8 recommendation). this allows the use of modem-optimized filter for v.34 and v.90 connections. if the duslic-e/-e2/-p utd dete cts that a modem connection is about to be established, the optimized filter co efficients for the modem connection can be downloaded before the modem co nnection is set up. with this mechanism implemented in the duslic-e/-e2/-p chip set, the opti mum modem transmission rate can always be achieved. figure 32 shows the functio nal block diagram of the utd unit: figure 32 utd functi onal block diagram initially, the input signal is filtered by a programmable band-pass filter (center frequency f c and bandwidth f bw ). both the in-band signal (upper path) and the out-of-band signal (lower path) are determined, and the absolu te value is calculated. both signals are furthermore filtered by a limiter and a low-pass filter. al l signal samples (absolute values) below a programmable limit lev n (noise level) are set to zero and all other signal samples are dimi nished by lev n . the purpose of this limiter is to increase noise robustness. after the limiter st ages, both signals are filtered by a fixed low-pass filter. the evaluation logic bl ock determines whether a tone interval or silence interval is detected and whether an inte rrupt is generated for the receive or transmit path. ezm14061 s utd programmable band-pass |x| |x| + + limit limit lp lp evaluation logic
duslic functional description preliminary data sheet 66 ds3, 2003-07-11 the utdr-ok or utdx-ok bit (register intreg3 on page 155 ) will be set if both of the following conditions hold for a time span of at least rtime 1) without breaks longer than rbrktime: 1. the in-band signa l exceeds a programmable level lev s . 2. the difference of the in-b and and the out-of-band sign al levels exceeds delta utd . the utdr-ok or utdx-ok bit will be reset if at least one of these conditions is violated for a time span of at least etime during which the violation continues for at least ebrktime. etime and ebrktime help redu ce the effects of sporadic dropouts. if the bandwidth parameter is programmed to a negat ive value, the utd unit can be used for the detection of silence in tervals in the entire frequen cy range. the duslic-e/-e2/-p utd unit is compatible with the itu-t g. 164 recommendation. t he utd is resistant to a modulation with 15 hz sinusoidal signals a nd a phase reversal, but is not able to detect the 15 hz modulation an d the phase reversal. 2.8.6 mips requirements for edsp capabilities table 8 shows the mips requirements fo r each algorithm using the edsp: attention: the maximum capability of the edsp is 32 mips. the user has to make sure that the sum of all enabled al gorithms does not exceed 32 mips in any case! 1) for rtime, rbrktime, etime and ebrktime see chapter 5.2.3.3 . table 8 mips requirements algorithm used mips conditions caller id sender (cis) 1.736*n cis n cis = 0...2 universal tone detection (utd) 1.208*n utd n utd = 0...4, transmit and receive for two channels dtmf receiver 6.296*n dtmf n dtmf = 0...2 line echo canceller (l ec) (3.536 + 0.032*len)*n lec n lec = 0...2 (for len see register lec-len on page 229 ) non linear processor (nlp) 1) 1) slicofi-2 version 1.5 only 2.448*n nlp n nlp = 0...2 operating system 1.432 ?
duslic functional description preliminary data sheet 67 ds3, 2003-07-11 example: all algorithms for all channels enabled and lec length = 8 ms (len = 64): 33.32 mips total co mputing load exceedin g the 32 mips limit! all algorithms for all channels enabled and lec length = 4 ms (len = 32): 31.272 mips total computing l oad within the 32 mips limit. 4 x utd, 2 x dtmf receiver and 2 x lec (8 ms) enabled: 29.85 mips total co mputing load within the 32 mips limit. example for slicofi-2 version 1.5 (with nlp): all algorithms for all channels enabled and lec length = 4 ms (len = 32): 36.344 mips total computing l oad exceeding the 32 mips limit! 2 x dtmf receiver, 2 x le c (8 ms) and 2 x nlp enabled: 30.1 mips total computing lo ad within the 32 mips limit. 2.9 message waiting indicat ion in duslic-e/-e2/-p message waiting indication (mwi) is usuall y performed using a glow lamp at the subscriber phone. current does not flow thro ugh a glow lamp unti l the voltage reaches a threshold value above approx imately 80 v. at this thresh old, the neon gas in the lamp will start to glow. wh en the voltage is reduced, the curr ent falls under a certain threshold and the lamp glow is extingu ished. duslic has high-volt age slic technology (170 v) that is able to activate the glow lamp without any external components. the hardware circuitry is shown in figure 33 . the figure shows a typical telephone circuit with the hook switch in the on-hook mode, togethe r with the impedances for the on-hook (z r ) and off-hook (z l ) modes. figure 33 mwi circuitry with glow lamp ezm14066 z l r mw z r z l ac impedance z r ringer impedance r mw pre resistor message waiting mw lamp
duslic functional description preliminary data sheet 68 ds3, 2003-07-11 the glow lamp circuit also requires a resistor (r mw ) and a lamp (mw la mp) built into the phone. when activated, the la mp must be able to either blink or rema in on constantly. in non-duslic-e/-e2/-p solutions, the tele phone ringer may respond briefly if the signal slope is too steep; behavior that is not desir able. the integrated ramp generator of the duslic-e/-e2/-p can be progra mmed to increase th e voltage slowly, to ensure that the lamp is activated and not the ringer. to activate the message wait ing function of duslic-e/- e2/-p, the following steps should be performed: 1. activating ring pause mode by setting the m0-m2 bits 2. select ring offset ro2 by setting the bits in register lmcr3 3. enable the ramp generator by sett ing bit ramp-en in register lmcr2 4. switch between the ring of fsets ro3 and ro2 in regist er lmcr3 to flash the lamp on and off (see figure 34 ). the values for ro2 and ro3 must first be programmed in the cram to the appropriate values so that the lamp will flash on and off. figure 34 timing diagram 2.10 three-party conferenci ng in duslic-e/-e2/-p each duslic-e/-e2/-p channel has a three- party conferencing facility implemented which consist of four pcm registers, adder s and gain stages in the microprogram and the corresponding cont rol registers (see figure 35 ). cascading duslic-e/-e2/-p channels allows multi-pa rty conferencing as well. ezm14067 v tr rng-offset bits v high v low power down state ring pause state t t lamp on lamp off 10 11 ro 3 ro 2
duslic functional description preliminary data sheet 69 ds3, 2003-07-11 this facility is available in pcm/ c mode only. the pcm control registers pcmr1 through pcmr4 and pcmx1 thr ough pcmx4 control the time slot assignment and pcm highway selection, while t he bits pcmx-en, conf-en, and confx-en in the bcr3 register control the behavior of the conferencing facility and the pcm line drivers (see figure 35 ). a programmable gain stag e g is able to adjust the gain of the conferencing voice data (b, c, d, s) in a ra nge from ?6 db to +3 db to pr event an overload of the sum signals. figure 35 conference block for one duslic channel note: g ? gain stage (gain facto r) set in cram coefficients, x1 - x4 ? pcm transmit channels, r1 - r4 ? pcm receive channels, a, b, c, d, s ? examples for voice data on pcm channe ls x1?x4, r1?r4. 2.10.1 conferencing modes table 9 conferencing mod es: receive channels configuration registers r eceive channels subscr. mode pcmx- en conf- en confx- en r1 r2 r3 r4 s pcm off 0 0 0 ????off pcm active 1 0 0 a???a ezm14069 + + + subscriber s pcm highways g g g conf_en = 0 1 0 conf_en = 0 0 1 subscribers pcm channel x4 x1 x3 x2 a r1 b r2 c r3 d r4 - - - x2=(r3?r4)*g x3=(r2?r4)*g x4=(r2?r3)*g
duslic functional description preliminary data sheet 70 ds3, 2003-07-11 (see also ?control of the active pcm channels? on page 126 ) external conference 001?bcdoff external conference + pcm active 101abcda internal conference 010?bc?g(b+c) table 10 conferencing mod es: transmit channels configuration registers t ransmit channels subscr. mode pcmx- en conf- en confx- en x1 x2 x3 x4 s pcm off 000offoffoffoffoff pcm active 100soffoffoffa external conference 001off g(c+d) g(b+d) g(b+c) off external conference + pcm active 101s g(c+d) g(b+d) g(b+c) a internal conference 010off g(c+s) g(b+s) off g(b+c) table 9 conferencing modes: receive channels (cont?d) configuration registers r eceive channels subscr. mode pcmx- en conf- en confx- en r1 r2 r3 r4 s
duslic functional description preliminary data sheet 71 ds3, 2003-07-11 pcm off after a reset, or in power down mode, ther e is no communication via the pcm highways. also, when selecting new time slots, it is recommended to switch off the pcm line drivers by setting the cont rol bits to zero. pcm active this is the normal operating mode without conferencing. only the channels r1 and x1 are in use, and voice data are transferred from subscriber a to analog subscriber s and vice versa. external conference in this mode, the slicofi-2 acts as a server for a three-party conference of subscribers b, c, and d that may be controlled by an y device connected to the pcm highways. the slicofi-2 channel itself can remain in powe r down mode to redu ce power consumption. external conference + pcm active as in external conference mode, any extern al three-party conferen ce is supported. at the same time, an internal phone call is active usin g the channels r1 and x1. internal conference if the analog subscriber s is one of the conference part ners, the internal conference mode will be selected . the partners (b, c) do not need any conference fa cility as the slicofi-2 performs all required functions for them as well. 2.11 16 khz mode on pcm highways in addition to the standard 8 khz transmission pcm inte rface modes, there are also two 16 khz modes for high-speed da ta transmission performance. table 11 and table 12 show the configuration of pcm channels for the different pcm interface modes (see ?control of the active pc m channels? on page 126 ).
duslic functional description preliminary data sheet 72 ds3, 2003-07-11 the configuration bits pcm16k and lin (in the bcr3 regist er) are used to select the following pcm interface modes: pcm mode normal mode used for voice transmissi on via channels r1 and x1 (receive and transmit). the pcm input channels r2, r3 and r4 are always available for use in different conference configur ations. the status of the pc m output channels depends on the conference mode configuration. lin mode similar to the pcm mode, but for 16 bit linear data at 8 k hz sample rate via the pcm channels r1, r1l (receive) and channels x1, x1l (transmit) . data are sent msb first, two?s complement. table 11 possible modes in pcm/c interface mode: receive channels mode configuration bits receive pcm channels pcm16k lin r1 r1l 1) r2 r3 r4 pcm 00a 2) bcd lin 0 1 a-hb a-lb b c d pcm16 10ds1??ds2? lin16 1 1 ds1-hb ? ds1-lb ds2-hb ds2-lb 1) time slot r1 + 1 2) empty cells in the table indicate unused data in the pcm receive channels and switched-off line drivers in the pcm transmit channels table 12 possible modes in pcm/c interface mode: transmit channels mode configuration bits transmit pcm channels pcm16k lin x1 x1l 1) x2 x3 x4 pcm 0 0 s ? depends on conference mode lin 0 1 s-hb s-lb depends on conference mode pcm16 10ds1??ds2? lin16 1 1 ds1-hb ? ds1-lb ds2-hb ds2-lb 1) time slot x1 + 1
duslic functional description preliminary data sheet 73 ds3, 2003-07-11 pcm16 mode mode for higher data transmi ssion rate of pcm encoded data using a 16 khz sample rate (only in pcm/ c interface mode with the pcmx-en bit in the bcr3 register set to one). in this mode, the chann els r1, r3 (x1, x3) are used to receive (transmit) two samples of data (ds1, ds2) in each 8 khz frame. lin16 mode like the pcm16 mode for 16 khz sample rate , but for linear data. channels r1 to r4 (x1 to x4) are used for receiv ing (transmitting) the high an d low bytes of the two linear data samples ds1 and ds2.
duslic operational description preliminary data sheet 74 ds3, 2003-07-11 3 operational description 3.1 overview of all duslic operating modes table 13 overview of all duslic operating modes slicofi-2x mode slic type cidd/ciop 1) additional bits used 2) slic-s/ slic-s2 slic-e/ slic-e2 slic-p m2 m1 m0 sleep (sl) ? pdrhpdrh111sleep-en=1 pdrr111sleep-en=1, actr=1 power down resistive (pdr) pdrh pdrhpdrh111sleep-en=0 pdrr111sleep-en=0, actr=1 power down high impedance (pdh) pdh pdh pdh 000? active high (acth) acth acthacth010? active low (actl) actl actl actl 010actl=1 active ring (actr) actr actractr010actr=1 ringing (ring) actr 3) actractr101? ? ? rot 101hit=1 ? ? ror 101hir=1 active with hit 4) hit hit hit 0 0 1 1 0 0 hit = 1 hit = 1, actr = 0 active with hir 5) hir hir hir 0 0 1 1 0 0 hir = 0 hir = 0, actr = 0 active with ring to ground rot 010hit=1, actr=1 active with tip to ground ror 010hir=1, actr=1 high impedance on ring and tip (hirt) ? hirt hirt 010hir=1, hit=1
duslic operational description preliminary data sheet 75 ds3, 2003-07-11 sleep (sl) ? only available with duslic-e/-e2/-p/-es/-es2 the slicofi-2 is able to go into sleep mode with minimal power dissipation. in this mode, off-hook detection is performed without any checks on spikes or glitches. the sleep mode can be us ed for either channel, but for the most effective power savings, both channels should be set to this mode. note that this r equires the following: if both channels are set to the sleep mode, only non-noi sy lines should be used due to the lack of persistence checking. wake up takes abo ut 1.25 ms, as the on-chip pll is also switched off. ther efore, it is also possible to switch off all external clocks. in this mode, no programming or other functionality is available. the off-hook event is indicated either by (1 ) setting the interrupt pin to low level, if the pcm/ c interface mode is selected, or (2) pu lling down the du pin, if iom-2 interface is used. if only one channel is se t to sleep mode, persisten ce checking and off-hook indication are performed as in any other m ode, but the off-hook level is fixed to 2 ma at the subscriber line. no sp ecial wake up is needed if on ly one channel is in sleep mode. a simple mode chan ge ends the sleep mode. a sleeping slicofi-2 wakes up if the cs pin is drawn to low level when the pcm/ c interface is used or if the mx bit is set to 0 when the iom-2 interface is used. note active with metering actx 3) 6) actx 4) actx 4) 1 1 0 ttx-dis to select reverse polarity or ttx metering ground start hit hit hit 1 1 0 0 0 0 ? actr = 0 ring pause actr 3) actr actr ror rot 001 hir = 1 hit = 1 1) cidd = data downstream command/indication channel byte (iom-2 interface) ciop = command/indication operation for further information, see ?slicofi-2x command structure and programming? on page 140 . 2) if not otherwise stated in th e table, the bits actl, actr, hit, hir must be set to 0. 3) only for slic-s 4) hit = high impedance on tip 5) hir = high impedance on ring 6) actx means acth, actl or actr. table 13 overview of all duslic operating modes (cont?d) slicofi-2x mode slic type cidd/ciop 1) additional bits used 2) slic-s/ slic-s2 slic-e/ slic-e2 slic-p m2 m1 m0
duslic operational description preliminary data sheet 76 ds3, 2003-07-11 that no programming is possi ble until the slicofi-2 wake s up. in iom-2 mode, the identification request can be used as a wake up signal as this command is independent of the inter nal clock. in the pcm/ c mode, it is re commended that cs be set to 0 for onl y one clock cycle. after a wake up from sleep mode, the sl icofi-2 enters the pdrh or pdrr mode. to re-enter sleep mode, it is necessary to first perform a mode change to any active mode on at least one channel. power down resistive (pdrh for slic-e/- e2/-s/-s2 and pdrh, pdrr for slic-p) the power down resistive mo de is the standard mode fo r none-active lines. off-hook is detected by a current value fed to the d sp, is compared wi th a programmable threshold, and is filtered by a data upstream persistence checker. the power management slic-p can be sw itched to a power down resistive high (pdrh) mode or to a power down resi stive ring (pdrr) mode. high impedance on ring and tip (hirt) the line drivers in the slic-e/-e2/-p are shut down and no resistor s are switched to the line. off-hook detection is no t possible. in hirt mode, the slicofi-2 is able to measure the input offset of the current sensors. power down high impedance (pdh) in power down high impedance mode, the slic is totally powered down . no off-hook sensing can be perfo rmed. this mode can be used for emergency shutdown of a line. active high (acth) a regular call can be performed, voice and me tering pulses can be transferred via the telephone line, and th e dc loop is operational in the active high mode using v bath . active low (actl) the active low mode is similar to the active high mode. the only difference is that the slic uses a lower battery voltage, v batl (bit actl = 1). active ring (actr) the active ring mode for the slic-e/-e2 is different from the acti ve ring mode for the slic-p. the slic-e/-e2 uses th e additional posi tive voltage v hr for extended feeding, whereas the slic-p switches to the negative battery voltage v batr .
duslic operational description preliminary data sheet 77 ds3, 2003-07-11 ringing if the slicofi-2x is switched to ringing mode, the slic is switched to actr mode. with the slic-p connecte d to the slicofi-2, the ring on ring (ror) mode allows unbalanced internal ri nging on the ring wire. the tip wi re is set to ba ttery ground. the ring signal will be superimposed by v batr /2. the ring on tip (rot) mode is equivalent to the ror mode. active with hit this is a testing mode where the tip wire is set to a high impedanc e mode. it is used for special line testing. it is only available in an active mode of the slicofi-2x to enable all necessary test features. active with hir hir is similar to hit but with the ring wire set to high impedance. active with metering any available active mode can be used for metering, with eith er reverse polarity or with ttx signals. ground start the tip wire is set to high impedance in ground start mo de. any current drawn on the ring wire leads to a signal on it, indicating off-hook. ring pause the ring burst is switched off in ring pause, but the slic remains in the specified mode and the off-hook recognitio n behaves the same as in ringing mode (ring trip).
duslic operational description preliminary data sheet 78 ds3, 2003-07-11 3.2 operating modes for the du slic-s/-s2/-se/-se2 chip set table 14 duslic-s/-s2/-se/-se2 operating modes slicofi-2s /slicofi-2s2 mode slic-s/s2 /slic-e/e2 mode slic-s/-s2 /slice/e2 internal supply voltages (+/?) [ v hi / v bi ] system functionality active circuits tip/ring output voltage pdh pdh open/ v bath none none high impedance power down resistive pdrh open/ v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) ? pdrhl 1) open/ v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) active low (actl) actl v bgnd / v batl voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v batl + v ac + v dc )/2 ring: ( v batl ? v ac ? v dc )/2 active high (acth) acth v bgnd / v bath voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v bath + v ac + v dc )/2 ring: ( v bath ? v ac ? v dc )/2 active ring (actr) actr v hr / v bath voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: (+ v bath + v hr + v ac + v dc )/2 ring: (+ v bath + v hr ? v ac ? v dc )/2
duslic operational description preliminary data sheet 79 ds3, 2003-07-11 ringing (ring) actr v hr / v bath balanced ring signal feed (including dc offset) buffer, sensor, dc loop, ring generator tip: ( v bath + v hr + v dc )/2 ring: ( v bath + v hr ? v dc )/2 ring pause actr v hr / v bath dc offset feed buffer, sensor, dc loop, ramp generator tip: ( v bath + v hr + v dc )/2 ring: ( v bath + v hr ? v dc )/2 hirt hirt v hr / v bath for example: sensor offset calibration sensor, dc transmit path high impedance active with hir hir v hr / v bath for example: line test (tip) tip buffer, sensor, dc + ac loop tip: ( v bath + v hr + v ac + v dc )/2 ring: high impedance active with hit hit v hr / v bath for example: line test (ring) ring buffer, sensor, dc + ac loop ring: ( v bath + v hr ? v ac ? v dc )/2 tip: high impedance 1) load external c for switching from pdrh to acth in on-hook mode. v ac ? tip/ring ac voltage v dc ? tip/ring dc voltage table 14 duslic-s/-s2/-se/-se2 operating modes (cont?d) slicofi-2s /slicofi-2s2 mode slic-s/s2 /slic-e/e2 mode slic-s/-s2 /slice/e2 internal supply voltages (+/?) [ v hi / v bi ] system functionality active circuits tip/ring output voltage
duslic operational description preliminary data sheet 80 ds3, 2003-07-11 3.3 operating modes for the du slic-e/-e2/-es/-es2 chip set table 15 duslic-e/-e2/-es/-es2 operating modes slicofi-2 mode slic-e/e2 /slic-s/s2 mode slic-e/-e2 /slic-s/s2 internal supply voltages (+/?) [ v hi / v bi ] system functionality active circuits tip/ring output voltage pdh pdh open/ v bath none none high impedance sleep pdrh open/ v bath off-hook detect via off-hook comparator off-hook, analog comparator v bgnd / v bath (via 5 k ? ) power down resistive pdrh open/ v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) ? pdrhl 1) open/ v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) active low (actl) actl v bgnd / v batl voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v batl + v ac + v dc )/2 ring: ( v batl ? v ac ? v dc )/2 active high (acth) acth v bgnd / v bath voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v bath + v ac + v dc )/2 ring: ( v bath ? v ac ? v dc )/2 active ring (actr) actr v hr / v bath voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: (+ v bath + v hr + v ac + v dc )/2 ring: (+ v bath + v hr ? v ac ? v dc )/2
duslic operational description preliminary data sheet 81 ds3, 2003-07-11 ringing (ring) actr v hr / v bath balanced ring signal feed (including dc offset) buffer, sensor, dc loop, ring generator tip: ( v bath + v hr + v dc )/2 ring: ( v bath + v hr ? v dc )/2 ring pause actr v hr / v bath dc offset feed buffer, sensor, dc loop, ramp generator tip: ( v bath + v hr + v dc )/2 ring: ( v bath + v hr ? v dc )/2 hirt hirt v hr / v bath for example: sensor offset calibration sensor, dc transmit path high impedance active with hir hir v hr / v bath for example: line test (tip) tip-buffer, sensor, dc + ac loop tip: ( v bath + v hr + v ac + v dc )/2 ring: high impedance active with hit hit v hr / v bath for example: line test (ring) ring-buffer, sensor, dc + ac loop ring: ( v bath + v hr ? v ac ? v dc )/2 tip: high impedance 1) load external c for switching from pdrh to acth in on-hook mode v ac ? tip/ring ac voltage v dc ? tip/ring dc voltage table 15 duslic-e/-e2/-es/-es2 operating modes (cont?d) slicofi-2 mode slic-e/e2 /slic-s/s2 mode slic-e/-e2 /slic-s/s2 internal supply voltages (+/?) [ v hi / v bi ] system functionality active circuits tip/ring output voltage
duslic operational description preliminary data sheet 82 ds3, 2003-07-11 3.4 operating modes for the duslic-p chip set table 16 duslic-p operating modes slicofi-2 mode slic-p mode slic-p internal supply voltages [ v bi ] system functionality active circuits tip/ring output voltage pdh pdh v batr none none high impedance sleep pdrh v bath off-hook detect via off-hook comparator off-hook, analog comparator v bgnd / v bath (via 5 k ? ) sleep pdrr v batr off-hook detect via off-hook comparator off-hook, analog comparator v bgnd / v batr (via 5 k ? ) power down resistive pdrh v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) ? pdrhl 1) v bath off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v bath (via 5 k ? ) ?pdrr v batr off-hook detect as in active mode (dsp) off-hook, analog comparator v bgnd / v batr (via 5 k ? ) ? pdrrl 2) v batr off-hook detect as in active mode (dsp) off-hook, dc transmit path v bgnd / v batr (via 5 k ? ) active low (actl) actl v batl voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v batl + v ac + v dc )/2 ring: ( v batl ? v ac ? v dc )/2 active high (acth) acth v bath voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v bath + v ac + v dc )/2 ring: ( v bath ? v ac ? v dc )/2
duslic operational description preliminary data sheet 83 ds3, 2003-07-11 active ring (actr) actr v batr voice and/or ttx transmission buffer, sensor, dc + ac loop, ttx generator (optional) tip: ( v batr + v ac + v dc )/2 ring: ( v batr ? v ac ? v dc )/2 ringing (ring) actr v batr balanced ring signal feed (including dc offset) buffer, sensor, dc loop, ring generator tip: ( v batr + v dc )/2 ring: ( v batr ? v dc )/2 ringing (ring) ror v batr ring signal on ring, tip on bgnd buffer, sensor, dc loop, ring generator ring: ( v batr ? v dc )/2 tip: 0 v ringing (ring) rot v batr ring signal on ring, tip on bgnd buffer, sensor, dc loop, ring generator tip: ( v batr + v dc )/2 ring: 0 v ring pause actr, ror, rot v batr dc offset feed buffer, sensor, dc loop, ramp generator tip: ( v batr + v dc )/2 ring: ( v batr ? v dc )/2 hirt hirt v batr for example: sensor offset calibration sensor, dc transmit path high impedance active with hir hir v batr for example: line test (tip) tip-buffer, sensor, dc + ac loop tip: ( v batr + v ac + v dc )/2 ring: high impedance active with hit hit v batr for example: line test (ring) ring-buffer, sensor, dc + ac loop ring: ( v batr ? v ac ? v dc )/2 tip: high impedance 1) load external c for switching from pdrh to acth in on-hook mode 2) load external c for switching from pdrr to actr in on-hook mode table 16 duslic-p operating modes (cont?d) slicofi-2 mode slic-p mode slic-p internal supply voltages [ v bi ] system functionality active circuits tip/ring output voltage
duslic operational description preliminary data sheet 84 ds3, 2003-07-11 3.5 reset mode an d reset behavior 3.5.1 hardware and power on reset a reset of the duslic is initiated by a po wer-on reset or by a hardware reset. hardware reset requires setting the signal at reset input pin to low level for at least 4 s. the reset input pin has a sp ike rejection that will safely su ppress spikes with a duration of less than 1 s. note: maximum spike rejection time is t rej, max . minimum spike rejection time is t rej,min . the slicofi-2x is reset by taking the reset line to low (see figure 36 ). during this time: all i/o pins are deactivated all outputs are inac tive (e.g. dxa/dxb) internal pll is stopped internal clocks are deactivated the chip enters the power down high impedance mode (pdh) when the reset is 1 (otherwise the chip is in a kind of reset mode that does not exactly equal the power down high impedance mode as the vcm voltage for the slic is missing) with the high going re set signal, the followi ng actions take place: clock detection pll synchronization reset routine runs when the reset routine has finished the chip is in power down impedance mode (pdh) the internal reset routine will then initiali ze the entire chip to default condition as described in the sop def ault register setting (see chapter 5 ). to run thro ugh the internal reset routine, it is necessa ry that all external clocks are supplied. the clocks are determined by the mode: c/pcm mode: fsc, mclk, pclk iom-2 mode: fsc and dcl. note: without valid and stable external clock signals, the duslic will not complete the reset sequence properly. the internal reset routine requires 12 frames (12 125 s = 1.5 ms) to be finished (including pll start up and cl ock synchronization) and requir es setting the default values given in table 17 . the first register access to the slicofi-2x may be performed after the internal reset routine is finished.
duslic operational description preliminary data sheet 85 ds3, 2003-07-11 figure 36 duslic reset sequence duslic_0016_reset_sequence t reset si gnal at pi n reset t rej (1 to 4 s) slicofi-2x internal reset routine mi n. 12*125 s = 1.5 ms first access to slicofi-2x possible (reset interrupt must be cl ear ed) . chi p i n power down hi gh i mpedance ( pdh) chip reset: - al l i/o pi ns deacti vated - al l outputs i nacti ve ( e.g. dxa/dxb) - i nter nal pll stopped - internal clocks deactivated
duslic operational description preliminary data sheet 86 ds3, 2003-07-11 3.5.2 software reset when performing a software rese t, the duslic runs the re set routine and sets the default settings of the conf iguration registers. the so ftware reset can be performed individually for each channel. table 17 default dc and ac values dc i k1 20 ma limit for constant current v k1 34 v voltage of limit betw een constant current and resistive zone k b 1 ? additional gain with extended battery feeding r i 10 k ? output resistance in constant current zone r k12 100 ? programmable resistance in resistive zone f ring 25.4 hz ring frequency a ring 62 vrms ring amplitude at tip/ring wire ro1 23 v ring offset voltage ro1 ro2 0 v ring offset voltage ro2 ro3 50 v ring offset voltage ro3 f ringlp 75 hz corner frequency of ring low-pass filter off-hookpd 2 ma current threshold fo r off-hook detection in power down mode off-hookact 8 ma off-hook detection in active with 2 ma hysteresis off-hookring 5 ma dc-current thresh old for off-hook detection in ringing mode off-hookmw 5 ma dc-current threshol d for off-hook detection in message waiting off-hookac 22 marms current threshold for ac ring trip detection linesup 5 ma current threshold li ne-supervision for ground start tip/ring 30 v voltage threshold at tip/ring wire for vtrlim bit dc-lowpass 1.2/20 hz dc low-pass se t to 1.2 and 20 hz respectively constramp 300 v/s slope of the ramp generator delay ring 0 ms delay of ring burst srend1 1/128 ? soft-reversal threshold 1 (referred to the input of the ramp generator)
duslic operational description preliminary data sheet 87 ds3, 2003-07-11 srend2 1/512 ? soft-reversal threshold 2 (referred to the input of the ramp generator) dup 10 ms data upstream persistence counter is set to 10 ms dup-io 16.5 ms data upstream pers istence counter for i/o pins, vtrlim and icon bits (regi ster intreg1) is set to 16.5 ms sr-time 80 ms time for soft-reversal ac im-filter 900 ? approximately 900 ? real input impedance th-filter th ger ? approximately complex german impedance for balanced network l x 0dbr relative level in transmit l r ?7 dbr relative level in receive attx 2.5 vrms teletax generator ampl itude at the resi stance of 200 ? f ttx 16 khz teletax generator frequency tg1 940 hz tone generator 1 (?12 dbm) tg2 1633 hz tone generator 2 (?10 dbm) ac-lm-bp 1004 hz ac level meter band pass table 17 default dc and ac values (cont?d)
duslic operational description preliminary data sheet 88 ds3, 2003-07-11 3.6 interrupt handling attention: even if interrupts are not used in the system application, the user has to clear the reset interrup t after each power-up reset. slicofi-2x provides extensive inte rrupt data for the host sys tem. interrupt handling is performed by the on-chip microprogram that handles the interrupts in a fixed 2 khz (500 s) frame. therefore, some delays up to 500 s can occur in the reactions of slicofi-2x , depending on when the host reads the interrupt registers. independent of the select ed interface mode (pcm/ c or iom-2), the general behavior of the interrupt is as follows: any change in one of the fo ur interrupt registers (at some bits, only transitions from 0 to 1) leads to an interrup t. the interrupt channel bit int- ch in intreg1 is set to 1 and all interrupt registers of one duslic channel are lock ed at the end of the interrupt procedure (500 s period). therefore, all changes within one 2 khz frame are stored in the interrupt registers. the lock remains until the inte rrupt channel bit is cleared (release interrupt by readin g all four interrupt regist ers intreg1 to intreg4 with one command). in iom-2 interface mode, the interrupt cha nnel bits are fed to the cidu channel (see iom-cidu). in pcm mo de, the int pin is se t to active (low). the interrupt is released (i nt-ch bit reset to 0) by reading all four interrupt registers by one command . reading the interrupt regi sters one-by-one using a series of commands does not release the inte rrupt even if all four registers are read. a hardware or power-on reset of the chip clears all pendi ng interrupts and resets the int line to inactive (pcm/ c mode) or resets the int-ch bit in cidu (iom-2 mode). the behavior after a software reset of both channels is similar, the interrupt signal switches to non-active within 500 s. a software reset of one duslic channel deactivates the interrupt sig nal if there is no active in terrupt on the other duslic channel. if the reset line is deactivated, a reset interrupt is generated for each channel (bit rstat in register intreg2). 3.6.1 recommended procedure for reading the interrupt registers when using slicofi-2, the followi ng procedure has to be applied: in case of an interrupt it is recommended to identi fy the interrupting ch annels first, before reading all four interrupt registers (see figure 37 ):
duslic operational description preliminary data sheet 89 ds3, 2003-07-11 figure 37 reading interrupt registers reading_ir read register intreg1 of channel a int-ch bit of channel a = 1? read all 4 interrupt registers of channel a with one sop read command read intreg1 of channel b int-ch bit of channel b = 1? read all 4 interrupt registers of channel b with one sop read command analyze interrupting event and react to interrupt (application specific: for example switch to active mode in case of an off-hook) end interrupt routine start interrupt routine yes yes no no
duslic operational description preliminary data sheet 90 ds3, 2003-07-11 3.7 power management and operating modes in many applications the power dissipated on th e linecard is a critical parameter. in large systems it is the mean power value (taking into account tra ffic statistics an d line length distribution) that determines cooling requir ements. on the other hand, particularly in remotely fed systems, the maxi mum power per line must be kept below a given limit. generally, system power dissipation is dete rmined primarily by t he high-voltage part. the most effective power-saving method thus is to optimize both sl ic functionality and supply voltage. this is primarily achi eved by using different operating modes. the three main modes (power down, acti ve and ringing) corre spond to the main system states: on-hook, signal transmission (voice, dtmf and/or ttx) and ring signal feed. power down off-hook detection is the only function available. it is achi eved by internally connecting 5k ? resistors from tip to bgnd and from ring to v bat . a simple sensing circuit supervises the dc current through these resistors (zero in on -hook and non-zero in off-hook state). this scaled transversal line current is transferre d to the it pin and compared with a programmabl e current threshold in the slicofi-2x . only the dc loop in the slicofi-2x is active. sleep mode in sleep mode both ac and dc loops are inactive. off-hook de tection, however, is still possible using an anal og comparator. for lowest powe r consumption th e clocks fed to the mclk and pclk pins also must be shut off. to change the duslic to another state, it must be wo ken up according to the procedure described in chapter 3.1 . active both ac and dc loops are o perative. the slic provides low-impedance voltage feed to the line. an integrated supply voltage switch allows to choose between two (slic-s/e) or even three (slic-p) different batt ery voltages, depend ing on loop length. ringing for internal ringing application s, the total supply range can be extended to 150 v to allow ring signals up to 85 vrms. whereas slic-s /e uses a positive supply vhr, the most negative battery voltage vbatr is intended for ringing with slic-p. the voltage capability is sufficient to drive very long lines at any ringer load and to reliably detect ring trip. for an overview of all duslic operating modes, see table 14 for peb 4264/-2, table 15 for peb 4265/-2 and table 16 for peb 4266.
duslic operational description preliminary data sheet 91 ds3, 2003-07-11 3.7.1 slicofi-2x power dissipation for optimized power consumption, unused ed sp functions must be sw itched off. typical power dissipation values for di fferent operating modes of the slicofi-2x can be found in the device data sheets. 3.7.2 slic power dissipation the slic?s power dissipat ion can be divid ed into two parts, the first arising from internal bias currents, the second being caused by any cu rrent fed to the line: p = p q + p o with p q = v dd * i dd + | v batl | * i batl + | v bath | * i bath + | v batr | * i batr + v hr * i hr [1] p o = (1.05 * v batx - v tr ) * i tr = 1.05 * v batx * i tr - r loop * i tr 2 [2] note: v batx is the relevant output st age supply voltage, whereas v tr , i tr and r loop denote line volt age, current and total line resistance, resp.. for any operating mode, the quiescent power dissipation p q (power at ze ro line current) thus is determined by the inte rnal supply currents as spec ified in the re spective slic data sheets ( i batr = 0 for slic-e/s, i hr = 0 for slic-p). signific ant design effort has been spent to keep them low. nevertheless, in typical active operations, the power component p o caused by the line current dominates. this power is dissipated in the output stages (to some small extent also in the current sensor) and is approximately proportional to the difference of respective supply voltage v batx and line voltage v tr . obviously, the be st way for power reduction is to keep the supply voltage as low as possible. 3.7.2.1 power down modes in all power down modes, th e internal bias currents are extremely small and no current is fed to the line. ev en with active off-hook detection, the result ing power dissipation of 5 mw is negligible. it is worth pointing out, that in large system s, due to the high percentage of inactive lines, this is the dominant factor for achieving a very low mean power value.
duslic operational description preliminary data sheet 92 ds3, 2003-07-11 3.7.2.2 active modes in all active modes, the total power dissipat ion usually is dominated by the line current part p o (eq. 2); the quiescent powe r typically is below 150 mw. for any line with total resistance r loop , the battery supply v batx has to fulfill the condition v batx > i tr,dc * r loop + v ac,pk + v drop v ac,pk peak value of ac signal v drop sum of voltage drops in slic output stage (typ. 2 v @ 20 ma) ideally, the supply voltage w ould be optimized individually for any line. this, however, is only possible at the expense of high effort, as it would require an highly efficient dc/dc converter per line. on the othe r hand, a single fixed vbat is determined by the longest loop (largest r loop ) to be served, and from eq. [2] would lead to very high power at short lines. a very efficient way to reduce short-loop power dissipatio n now is to use a second, lower battery supply voltage ( v batl ) whenever line resistance is small enough. this method is supported on all slics by the inte gration of a battery switch (slic-p even allows the use of 3 battery voltages). the e fficiency is demonstrated in figure 38 comparing typical total active power dissipatio n values for a 20 ma line cu rrent as a function of loop resistance for single -48 v (dotted) and do uble -48/-24 v (solid) ba ttery voltages, resp.. figure 38 typical slic power dissipation 0 200 400 600 800 1000 1200 0 500 1000 1500 2000 r loop [ ? ] p [mw] slic_power_diss
duslic operational description preliminary data sheet 93 ds3, 2003-07-11 3.7.2.3 ringing mode basically the considerations above are also valid in ring ing mode. the only difference results from the fact, that in ringing a large sinusoidal sig nal is applied to a complex rc load (compared with dc drive of an ohmic load in ac tive modes). eq. [2] is still valid, but obviously p o now is time dependent du e to the time dependence of both ringing voltage vtr and the resulting loop current. if the total load impedance (loop resistance plus ri nger load) is denoted as z l =| z l |*e j = r loop + r ring + 1 / j c ring calculation of the aver age ring power yields p o = (4 * v batx - * v ring,pk * cos ) * v ring,pk / (2 * * z l ) here v batx again denotes the total battery supply voltage. the minimum value can be derived from the condition v batx > v ring,pk + v ring,dc + v drop = v ring,rms * crest factor + v ring,dc + v drop the crest factor is th e ratio of peak and rms value (her e 1.41, as sinusoidal ringing is assumed). v ring,dc superimposed dc voltage for ri ng trip detection (10 to 20 v) v drop sum of voltage drops in slic output stage (typ. 2 v @ 20 ma) v ring,pk / rms peak / effective ring vo ltage at tip/ring pins as the resulting v batx for ringing typically is significantly larger than in active transmission modes, the total supply range is increased by either using an additional positive supply v hr (so v batx = v hr - v bath for slic-s/e) or providing a third battery voltage v batr ( v batx = v batr for slic-p). again, to minimize power dissipation, v batx has to be kept as low as possible. in ringing, however, the voltage at the ringer rather th an at the tip/ring pins is decisive. due to voltage division betw een ringer and line, the worst case for v batx is represented by maximum ringer load (mini mum ringer impedance, e.g 5 us ren) at maximum loop length. the above calculation is valid for power di ssipation during the ring burs t. the power values cover a broad range from typically 1 w to 3 w , mainly dependi ng on the ringer load. the mean ring power th en can be calculated by aver aging over the burst / pause cycle. so for a typical ringing cadence (1 second on and 4 se conds off) power is given by p average =k* p ring + (1 ? k) * p ringpause with k = 0.20
duslic operational description preliminary data sheet 94 ds3, 2003-07-11 3.8 integrated test and di agnostic functions (itdf) 3.8.1 introduction subscriber loops are affected by a variety of failures that must be monitored. monitoring the loop requires access to the subscriber lo op and requires test equipment in place that is capable of performing ce rtain specific measurements. the tests involve measurement of resistance, capacitance, leakage, a nd any interfering currents and voltages. 3.8.1.1 conventional line testing conventional linecards in central office (co) applications usuall y need two test relays per channel to access th e subscriber loop with the approp riate test equipment. one relay (test-out) connects the actual test unit to the local loop. all required line tests can be accomplished that way. the se cond relay (test-in) separates the local loop from the slic and connects a terminat ion impedance to it. hence, send ing a tone signal allows the entire loop to be checked, including the slicofi-2x and slic. 3.8.1.2 duslic line testing the duslic chip set uses its integrat ed test and diagnostic functions (itdf) to perform all tests necessary for monitoring the lo cal loop without an exte rnal test unit and test relays. the fact that measurements c an be accomplished much faster than with conventional test ca pabilities makes an even more co mpelling argument for the use of the duslic chip set. with the duslic, line tests on both channe ls can be performed concurrently, which also has a tremendous impa ct on the test time. all in all, the duslic increases the quality of service and redu ces the costs in va rious applications. figure 39 duslic line testing line testing duslic-s duslic-s2 duslic-e duslic-e2 duslic-p yes yes yes yes yes line failure co ? duslic_0025_ linetesting
duslic operational description preliminary data sheet 95 ds3, 2003-07-11 3.8.2 diagnostics duslic incorporates signal g enerators and test features implemented to accomplish a variety of diagnost ic functions. the slicofi-2x device generates all test signals, processes the informati on that comes back from the slic , and provides the data to a higher level master device, such as a microprocessor. all the tests can be initiated by the microprocessor and the results ca n be read back very easily. 3.8.2.1 line test capabilities the line test comprises the following functions: loop resistance leakage current tip/ring leakage current tip/gnd leakage current ring/gnd ringer capacitance line capacitance tip/ring line capacitance tip/gnd line capacitance ring/gnd foreign voltage me asurement tip/gnd foreign voltage me asurement ring/gnd foreign voltage measurement tip/ring measurement of ringing voltage measurement of line feed current measurement of supply voltage v dd of the slicofi-2x measurement of transvers al- and longitu dinal current two main transfer paths (level metering) are implemented to accomp lish all the different line measurement functions (refer to figure 40 ). 3.8.2.2 integrated signal sources the signal sources availabl e on the duslic chip set are: constant dc voltage (three progra mmable ringing dc offset voltages) refer to the cram coeffici ent set and register lmcr 3 (bits rng-offset[1:0]) on page 185 for more information. 2 independent tone ge nerators tg1 and tg2: refer to the cram coeffici ent set and register dscr (bits ptg, tg2-en, tg1-en) on page 179 for more information. ttx metering signal generator (12/16 khz) refer to the cram coefficient set and register bcr2 (bits ttx-dis, ttx-12k) on page 170 for more information. ramp generator (used for capacitance measurements) refer to the cram coefficient set and register lmcr2 (bit ramp-en) on page 183 .
duslic operational description preliminary data sheet 96 ds3, 2003-07-11 ring generator (5 hz - 300 hz) refer to the cram coefficient table 35 "cram coefficients" on page 205 . figure 40 shows the entire le vel metering block for ac and dc: figure 40 level metering block diagram duslic_0010_level_meter_block ttx adaptive filter result reg mux mux voice path shift factor k intdc offset register rectifier on / off + 2 k h z + / - 1 9 b i t progr gain stage deci- mation a / d 1 bit sigma delta 1 mhz dc prefi io4 - io3 offset vdd mux it il io3 io4 dc output voltage v dc on dcn ? dcp a-b a-b integrator 1x16ms ... 16x16ms shift factor k intac ac prefi a / d sigma delta 4 mhz decimation bandpass notch filter voice path pcm in: receive data from pcm or iom-2 interface + rectifier mux ac levelmeter itac a b a b c programmable not programmable lmcr2: lm-sel[3:0] lmcr1: dc-ad16 lmcr2: lm-rect lmcr3: lm-itime[3:0] lmcr2: lm-sel[3:0] cram lmcr2: lm-notch lm-filt ofr1/2 lmcr2: lm-sel[3:0] lmres1/2 lmcr1: lm2pcm lmcr1: lm-en cram cram cram 16 / 1 dc levelmeter integrator (ring period) pcm out: transmit data to pcm or iom-2 interface ttx real ttx img. c lmcr2: lm-sel[3:0]
duslic operational description preliminary data sheet 97 ds3, 2003-07-11 3.8.2.3 result register data format the result of any measurement can be read via the result registers lmres1/2. this gives a 16-bit value, with lm res1 being the high and lmr es2 being the low byte. the result is coded in 16 -bit twos complement: 3.8.2.4 using the level metering integrator both ac and dc level metering allows use of a programmable int egrator. the integrator may be configured for a single meas urement or to run continuously. see figure 41 through figure 43 . single measurement sequenc e (ac & dc level metering) figure 41 single measurement se quence (ac & dc level metering) table 18 level metering result value range negative value range positive value range ?full scale +full scale 0x8000 0xffff 0 0x7fff ?32768 ?1 0 +32767 lmcr1: lm-en intreg2: lm-ok int. period int. period start new measurement read result lmres1/2 lmcr1: lm-once = 1 duslic_0019_lm_single
duslic operational description preliminary data sheet 98 ds3, 2003-07-11 continuous measurem ent sequence (dc level metering) figure 42 continuous me asurement sequence (dc level metering) continuous measurem ent sequence (ac level metering) figure 43 continuous me asurement sequence (ac level metering) duslic_0020_lm_contdc lmcr1: lm-en intreg2: lm-ok int. period int. period read result lmres1/2 lmcr1: lm-once = 0 int. period int. period read result lmres1/2 read result lmres1/2 500 s 500 s 500 s duslic_0021_lm_contac lmcr1: lm-en intreg2: lm-ok int. period int. period read result lmres1/2 lmcr1: lm-once = 0 500 s 500 s 500 s int. period read result lmres1/2 read result lmres1/2 1 ms 1 ms
duslic operational description preliminary data sheet 99 ds3, 2003-07-11 the integrated test and diagn ostic functions of the duslic allow to do measurements with and without an in tegrator. a measurement with the integrator is started by setting the bit lm-en in regist er lmcr1 from 0 to 1. figure 44 timing lm-ok bit when using the integrator for doing levelmeter measurements, the lm-ok bit in register intreg2 is used to indicate if the integration has started or is finished, respectively. after the bit lm-ok is set to 1 again, the result regist ers can be re ad to get the measurement result. figure 44 shows the timing of the bit lm-ok in re lation to the start of the integration period (transition of lm-en from 0 to 1) and in relation to a valid result in the result registers. the user control software must take care of the m entioned timing relationship: 1. after starting the integrator by setting bit lm-en from 0 to 1, th e bit lm-ok could still be set to 1 from a previous measurement, which would indica te the end of the integration period whil e the actual integrati on is still going on. ?with slicofi-2x version 1.5, the firm ware must wait at least 1 ms before polling the bit lm-ok. 2. after the integration is finished, the bit lm -ok is set to 1 by slicofi-2x . ?with slicofi-2x version 1.5, the lm-ok bit is set to 1 synchronous with the availability of the lm result. therefore no delay is necessary before reading the levelmeter result registers. timing_lm-ok lm-en lm-ok read lm result register after bit lm-en is set from 0 to 1, bit lm-ok can still be 1 from a previous measurement: - slicofi-2 v1.5: 1000 s delay until bit lm-ok is set to 0. integration period
duslic operational description preliminary data sheet 100 ds3, 2003-07-11 3.8.2.5 dc level metering the path of the dc leve l meter is shown in figure 40 . hereby, the dc le vel meter results will be determined and pr epared depending on certain configuration settings. the selected input signal beco mes digitized after pre-filt ering and analog-to-digital conversion. the dc leve l meter is selected a nd enabled as shown in table 19 : the effective sampling rate after the decimation stages is 2 khz. the decimated value has a resolution of 19 bits. the offset compensation value (see chapter 3.8.2.8 ) within the offset registers ofr1 (bits offset-h[7 :0]) and ofr2 (bits offset-l[7:0]) can be set to eliminate the of fset caused by the slic current sensor, pr e-filter, and analog-to- digital converter. after the summation point the signal pa sses a programmable digital gain filter. the addition al gain factor is either 1 or 16 depending on re gister lmcr1 (bit dc-ad16): lmcr1 (bit dc-ad16) = 0: no additional gain factor lmcr1 (bit dc-ad16) = 1: additional gain factor of 16 the rectifier after th e gain filter can be turned on/off with: lmcr2 (bit lm-rect) = 0: rectifier disabled lmcr2 (bit lm-rect) = 1: rectifier enabled a shift-factor k intdc in front of the integrator pr events the level meter during an integration operation to create an overflow. if an overfl ow in the level meter occurs, the output result will be full scale (see table 18 ). if the shift factor k intdc is set to e.g. 1/8, the content of th e level meter resu lt register is the integration resu lt divided by 8. table 19 selecting dc level meter path lm-sel[3:0] in register lmcr2 dc level meter path 0100 dc out voltage on dcp-dcn 0101 dc current on it 1001 dc current on il 1010 voltage on io3 1011 voltage on io4 1101 v dd 1110 offset of dc-pre-filter (shor t circuit on dc-p re-filter input) 1111 voltage on io4 ? io3
duslic operational description preliminary data sheet 101 ds3, 2003-07-11 the shift factor k intdc is set in the cram (offset address 0x76): cram: address 0x76: lmdc2/lmdc1 address 0x77: 0/lmdc3 lmdc1, lmdc2 and lmdc3 are 4- bit nibbles which contain k intdc . duslicos allows automatic calcul ation of the coefficients for k intdc for i trans measurement. the according parameter is "dc levelmeter current 50% full scale" (see duslicos dc control parameters 4/4). the setting of this pa rameter affects the shift factor (k intdc ) of the dc levelmeter. the set current will result in 50% full scale of the levelmeter result registers if the integration of the dc leve lmeter is done over the integration period determined by the ring freque ncy. example: if the dc leve lmeter current 50% full scale is set to 2 ma and the actual current to be measured is 3 m a, the value of the levelmeter result register is 24575 d (75% full scale). duslicos uses finer steps as the examples listed in table 20 . if the user wants to set the k intdc factor manually, the listed steps should be sufficient. the expected ?current for ring off-hook detection? (see duslicos dc control parameter 2/4) of 20 ma, fo r example, is entered in to the program and then k intdc is automatically calculated to ac hieve 50 % full scale if the cu rrent of 20 ma is integrated over the set ringer period. the integration function accumu lates and sums up the level meter values over a set time period. the time period is determined by the programmed ring frequency. a ring frequency f ring of 20 hz results in 100 samples (n samples ), because of the 2 khz effective dc sampling rate f s,dc . the number of inte gration samples n samples may also be programmed directly by accessing dedicated bytes in the coefficient ram (cram). table 20 k intdc setting table lmdc1 lmdc2 lmdc3 k intdc 8801 881? 88:: 8861/64 8871/128 n samples f sdc , f ring --------------- 2000hz f ring -------------------- - ==
duslic operational description preliminary data sheet 102 ds3, 2003-07-11 cram: address 0x73: rgf2/rgf1 address 0x74: rga1/rgf3 rgf1, rgf2 and rgf3 are 4-bit nibbles which cont rol the ring frequency f ring. rga1 is a 4-bit nibble that is calculated by duslicos and which controls the ringer amplitude (see duslicos by te file). to ensure that rga1 is not changed, please perform a read/modify/write operation. the integration function can be turned on and off by bit lm-en in register lmcr1. the level meter result of the se lected signal source will be st ored in the result registers lmres1 (bits lm-val-h[7:0]) and lmres2 (bits lm-val-l[7 :0]) depending on the lm-sel[3:0] bits in register lmcr2. the re sult registers get fr equently updated every 500 s if bit lm-en in register lmcr1 = 0, or a fter an integration period, if bit lm-en in register lmcr1 = 1. if the bit lm-once in register lmcr1 is set to 1, then the integration is executed only once. to start again, bit lm-en must be changed from 0 to 1. the level meter source/result can be transf erred to the pcm/iom- 2 interface, depending on the bit lm2pcm in register lmcr1. table 22 shows the level meter results without and with integrat or function. the integrator is enabled if bi t lm-en in register lmcr1 = 1. the level meter result lm value is a 16 bit twos complement value of lm-val-h[7:0] and lm-val-l[7:0]. the factor lm result used in table 22 is defined: example for posi tive value of lm result : lm-val-h = ?0010 0100" = 0x24 lm-val-l = ?1010 0101" = 0xa5 lm value = 0x24a5 = 9381 table 21 n samples setting table rgf1 rgf2 rgf3 f ring n samples 8805004 8812508 88::: 8867.81256 8873.91512 lm result lm value 32768 --------------------- - =
duslic operational description preliminary data sheet 103 ds3, 2003-07-11 lm result = 0.2863 example for negative value of lm result : lm-val-h = ?1001 1001" = 0x99 lm-val-l = ?0110 0010" = 0x62 lm value = 0x9962 = ?26270 lm result = ?0.8017 table 22 level meter re sults with and without integrator function lm-en = 0 (without integrator ) lm-en = 1 (with integrator) i trans 1) : power down resistive 1) dc current on pin it (bits lm-sel[3:0] = 0101) i trans 1) : any other mode i long 2) voltage: io3 3) , io4 4) , io4-io3 5) v dd v dc 6) with actl, acth v dc 6) with actr, ringing mode i trans lm result k it pdr , r it2 --------------------------- - v ad = i trans lm result 7.966 ma = i trans lm result k it pdr , v ad r it2 n samples k intdc ----------------------------------------------------------------------------------- = i trans lm result 7.966 ma n samples k intdc ------------------------------------------------------------- - = i trans lm result k it r it2 ----------- - v ad = i trans lm result 79.66 ma = i trans lm result k it v ad r it2 n samples k intdc ----------------------------------------------------------------------------------- = i trans lm result 79.66 ma n samples k intdc ------------------------------------------------------------- - = i long lm result ? k il r il --------- - v ad = i long lm result 67.7 ma ? = i long lm result k il v ad r il n samples k intdc ------------------------------------------------------------------------------- ? = i long lm result 67.7 ma n samples k int dc ------------------------------------------------------------ - ? = v input lm result v ad ? = v input lm result v ad n samples k intdc ------------------------------------------------------------- - ? = v dd lm result 3.9 v ? = v dd lm result 3.9 v n samples k int dc ------------------------------------------------------------ - ? = v dc lm result 76.35 v ? = v dc lm result 76.35 v n samples k int dc ------------------------------------------------------------ - ? = v dc lm result 152.7 v ? = v dc lm result 152.7 v n samples k int dc ------------------------------------------------------------ - ? =
duslic operational description preliminary data sheet 104 ds3, 2003-07-11 note: measurement of pins il , io3, io4, io4-io3 and v dd can cause problems in the dc loop. the measured value is always interpreted as i trans current. this can disturb the dc regulation a nd the off-hook indication. in active mode, the output of the dc loop can be froz en by setting the bit dc-hol d to 1. in ringburst mode, it is possible for duslic to automaticall y switch back to ringpause mode if the measurement result was in terpreted as off-hook. this can be avoided by programming the off-hook current to the maximum value (79.66 ma). measurement of ac signals via dc level meter this method is applicable for a single frequency si nusoidal ac signal that is superimposed on a dc signal. 1. set the ring frequency f ring to the frequency of the sign al to be measured. multiples of the expected signal peri od may also be used. 2. set the offset registers ofr1 and ofr2 to 0x00. 3. measure the dc contents with disa bled rectifier (bit lm-rect = 0). the dc contents can be ca lculated as described in table 22 . note: if there was an overflow inside the integrator during the integration period, the result will be full scale. reduce the shift factor k intdc or the number of samples n samples and start the measurement again. 2) dc current on pin il (bits lm-sel[3:0] = 1001) 3) voltage on io3 referenced to v vcm (typical 1.5 v) (bits lm-sel[3:0] = 1010) 4) voltage on io4 referenced to v vcm (typical 1.5 v) (bits lm-sel[3:0] = 1011) 5) voltage on io4 ? io3 referenced to v vcm (typical 1.5 v) (bits lm-sel[3:0] = 1111) 6) dc output voltage at slic measured via dcn ? dcp (bits lm-sel[3:0] = 0100) k intdc shift factor (see table 20 ) k it,pdr value of the current divider in power down resistive mode 5 k it value of the current divide r for transversal current 50 k il value of the current divider for longit udinal current 100 r it2 sense resistor for transversal current 680 ? r il sense resistor for l ongitudinal current 1600 ? v ad voltage at a/d converter referred to digital full scale 1.0834 v dc dc output voltage at sl ic measured via dcn ? dcp
duslic operational description preliminary data sheet 105 ds3, 2003-07-11 4. the offset registers of r1 and ofr2 must be programmed to the value where ofr1 is the hi gh byte and ofr2 is the low byte of the 16 bit word offset. 5. repeating the measurem ent of the dc content should re sult in a lm value of zero. 6. perform a new measurement with the rectifier enabled (bit lm-rect = 1). the result is the rectified mean value of the measur ed signal an can be calculated with the formulas of table 22 . 7. from this result, the peak value and the rms value can be calculated: 3.8.2.6 ac level meter the ac level meter is select ed and enabled as shown in table 23 : figure 40 on page 96 shows the path of the ac/ttx le vel meter functions. the ac level meter allows access to the vo ice signal while the active voice signal is being processed. the input signal for the ac le vel meter might get processe d with a programmable filter characteristic, such as a bandpass- or notch filter. dep ending on the following settings, the bandpass or notch filter is turned on or off: register lmcr2 bit lm-filt = 0: no filter enabled (n ormal operation) register lmcr2 bit lm-filt = 1: band pass/notch filter char acteristics enabled register lmcr2 bit lm-notch = 0: notch f ilter enabled, bandpass filter disabled register lmcr2 bit lm-notch = 1: bandpa ss filter enabled, notch filter disabled the rectifier cannot be turned o ff, it is always active in the ac path. a shift-factor in front of the integrator prevents the level meter from creating an overflow during an integration operation. the shift-factor can be set by the coeffi cient lm-ac gain (see cram coefficient set table 35 "cram coeffi cients" on page 205 ). table 23 selecting ac level meter path lm-sel[3:0] in register lmcr2 ac level meter path 0000 ac level meter in transmit 0110 ac level meter in receive 0111 ac level meter receive + transmit offset lm value n samples k intdc ------------------------------ ------------------------------ - ? = v peak v mean 2 ----------------------------- - = v rms v peak 2 --------------- =
duslic operational description preliminary data sheet 106 ds3, 2003-07-11 k intac can be set via coefficient lm-ac: cram: address 0x34: cg1/lm-ac lm-ac is a 4-bit nibb le which contains k intac. cg1 is a 4-bit nibble that is calculated by duslicos and which controls the conference gain (see duslicos byte file). to ensure that cg1 is not cha nged, please perform a read/modify/write operation. the integration function accumu lates and sums up the level meter values over a set time period. the time period from 1*16 ms to 16 *16 ms is set by the bits lm-itime[3:0] in register lmcr3. the integration function can be turned on and off by bit lm-en in register lmcr1. the number of samples n samples for the integrator is defined by: n samples = lm-itime * 8000 the level can be calculated by: the result registers get freq uently updated after an integr ation period, if bit lm-en in register lmcr1 = 1. if the bit lm-once in regi ster lmcr1 is set to 1 then the integration is executed only once. to start again, bit lm-en must be changed from 0 to 1. the level meter result can be transferred to the pcm/iom-2 interface, depending on bit lm2pcm in register lmcr1. measurement of cu rrents via itac to take current measurements via pin itac, all feedback loops (im-f ilters and th-filters) should be disabled. to simplify the form ulas, the programmable receive and transmit gain is disabled. this is done by setti ng the following bits: table 24 k intac setting table lm-ac k intac 01 1? :: 61/64 7 1/128 u dbm0 20 lm result 2k int n samples -------------------------------------------------------------- - ?? ?? log 3.14 + =
duslic operational description preliminary data sheet 107 ds3, 2003-07-11 register bcr4: ar-dis = 1, ax-dis = 1, th-dis = 1, im-dis = 1, frr-dis = 1, frx-dis = 1 register tstr4: opim-an = 1, opim-4m = 1 register lmcr1: test-en = 1 this setting results in a rece ive gain of 11.88 db caused by the internal filters. based on this, a factor k ad (analog to digital) can be defined: transversal current i rms measured at slic: to prevent overloading the analog input, the maximum ac transversal current may not be higher than 9 ma rms. usage of tone genera tor as signal source to simplify the formulas, t he programmable receive and tr ansmit gain is disabled. this is done by setti ng the following bits: register bcr4: ar-dis = 1, ax-dis = 1, th-dis = 1, im-dis = 1, frr-dis = 1, frx-dis = 1 register tstr4: opim-an = 1, opim-4m = 1 register lmcr1: test-en = 1 the tone generator level is influenced by a factor k tg , which is set in the tone generator coefficients. the internal fi lter attenuation is 2.87 db. r itac sense resistor for ac transversal current (r it1 +r it2 )1150 ? k ad constant factor from an alog to digital 3.272 v ?1 v adc voltage at a/d converter referr ed to digital full scale 1.2 v k it value of the current divide r for transversal current 50 k ad 10 filter ad 20 ------------------- - v adc ---------------------- 10 11.88 20 -------------- - 1.2 v ------------------ 3.272 v 1 ? === rms lm result k it k ad r itac k intac n samples 22 ---------------------------------------------------------- ------------------------------------------------------------ - lm result k intac n samples --------------------------------------------------- 14.76 m a == k da v dac 10 ?2.87 20 -------------- - trapez 2 ------------------- - k ac slic , 1.2 10 ?2.87 20 -------------- - 1.05 2 --------- - 6 ==
duslic operational description preliminary data sheet 108 ds3, 2003-07-11 output voltage bet ween tip and ring: v out =k da *k tg the bytes below are vali d for tone generator tg1 an a frequency of 1000 hz. cram: address 0x38: 0x08 address 0x39: t11g/0 address 0x40: t13g/t12g address 0x41: 0x05 address 0x42: 0xb3 address 0x43: 0x01 t11g, t12g and t13g are 4-bit nibbles which control the amplitude of the tone generator tg1. 3.8.2.7 level meter threshold a threshold can be set for the level meter re sult. when the result exceeds the threshold, then bit lm-thres in register intreg 2 is set to 1. it is also possible to activate an interrupt when the lm-thres bit changes by setting th e bit lm-thm (level meter threshold mask bit) in register lmcr2 to 0. k da constant factor from di gital to analog 3.84 vrms k ac,slic amplification factor of the slic 6 v dac voltage at d/a converter referr ed to digital full scale 1.2 v trapez crest factor of th e trapezoidal signal 1.05 table 25 k tg setting table t11g t12g t13g k tg 8917/8 808? 818? 8:8: 8581/64 8681/128 8781/256
duslic operational description preliminary data sheet 109 ds3, 2003-07-11 the level meter threshold can be calculat ed with duslicos or may be taken from table 26 . cram: address 0x2c: lmth2/lmth1 address 0x2d: 0/lmth3 (lmth1, lmth2 and lmth 3 are 4 bit nibbles) table 26 threshold setting table lmth1 lmth2 lmth3 threshold 1 0 0 75.0 % 0 1 0 62.5 % 8 8 0 50.0 % 8 9 0 37.5 % 9 0 0 25.0 % 8 1 0 12.5 % 8000.0%
duslic operational description preliminary data sheet 110 ds3, 2003-07-11 3.8.2.8 current offset error compensation the current offset error ca used by the current sens or inside the slic can be compensated by programming the co mpensation registers ofr1 and ofr2 accordingly. the current offs et error can be measured wi th the dc level meter. the following settings are nece ssary to accomplish this: the duslic must be set into the hirt mode by setting the bits hir and hit in register bcr1 to 1. in hirt mode, the line-drive rs of the slic are shut down and no resistors are switched to the line. as a matter of fact, no current is present in that mode, but the current sensor wrongly indicates a curr ent flowing (current offset error). the dc path for i trans current level meter must be selected by setting the lm-sel[3:0] bits in regi ster lmcr2 to 0101 (see table 19 ). the offset registers ofr1 a nd ofr2 must be set to 0000h. i off-err can be calculated like shown for ?i trans : any other mode? in table 22 (see the example below). the current offset error can be eliminated by programming the offset registers ofr1 and ofr2 according to the inverse value of the measured curre nt offset error. example: k intdc =1, n samples = 256, lm value = 0x0605 = 1541 short form: ofr1 = offset-h = 0xff ofr2=offset-l=0xfa lm result lm value 32768 --------------------- - 1541 32768 ---------------- 0.047 === i off err ? lm result 79.66 ma n samples k intdc ----------------------------- ------------------------------- - 0.047 79.66 ma 256 1 ------------------------- 0.0146 m a === o ffset i off err ? 79.66 ma ------------------------- 32768 ? 0.0146 ma 79.66 ma ---------------------------- - 32768 ? 6 ? 0xfffa == = offset lm value n samples k intdc ------------------------------ ------------------------------ - ? =
duslic operational description preliminary data sheet 111 ds3, 2003-07-11 3.8.2.9 loop resistance measurements the dc loop resistance can be determin ed by supplying a cons tant dc voltage v tr,dc to the ring- and tip line and measuring the dc loop current via it pin. the following steps are necessary to accomplish this: program a certain ring offset voltage ro 1, ro2, ro3 (see duslicos dc control parameter 2/4). select ring offset voltage rn g-offset[1:0] in register lm cr3 either to 01, 10 or 11. if 00 is selected, the dc regulation would be still ac tive and would not allow resistance measurement. choose an operation mode , either active high (acth) or ring pause. select the dc path for level meter by sett ing the bits lm-sel[3 :0] in register lmcr2 to 0101 (dc current on it). the transversal current can be determined by re ading the level mete r result registers lmres1, lmres2. based on the known cons tant output voltage v tr,dc (dc voltage according to rng-offset[1:0]) and the measured i trans current, the resistance can be calculated. it should be not ed that the calculated resi stance includes also the onboard resistors r prot and r stab . in order to increase the a ccuracy of the result, either the current offset can be compensated or the measurement can be done differentially. the latter approach eliminates the current - and voltage offsets. figure 45 shows an example circuit fo r resistance measurement: figure 45 example resi stance measurement duslic_0011_measurement_tip_ring slic slicofi-2x it il dc p dc n linecard r prot + r stab v tr,dc * line current sense signal to be measured i line r prot + r stab r line * dc offset voltage according to rng-offset[1:0]
duslic operational description preliminary data sheet 112 ds3, 2003-07-11 assumption: loop resistance r loop =1000 ? ; r loop =r line +2*r prot +2*r stab ring offset ro2 = 60 v (cram coefficient set accordingly). ring offset ro2 is selected by setting bits rn g-offset[1:0] in register lm cr3 to 10. the exact value for the ring offset voltage ca n be determined from the *.re s result file generated by duslicos during the calculation of the appropriate coefficients. select active high (acth) mode by se tting the line mode command cidd/ciop bits m2, m1, m0 to 010. in acth mode half of the ring offset voltage ro 2 of e.g. 60 v will be present and applie d to ring and tip. sequence to determine th e loop resistance r loop differentially: select dc level meter by se tting bits lm-sel[3:0] in register lmcr2 to 0101. read level meter result registers lmres1, lmres2. switch into reverse polarit y mode by setting bit revpo l in register bcr1 to 1. read level meter result registers lmres1, lmres2. if the loop resistor connected between ring and tip is 1000 ? (r line +r prot +r stab ), the expected current will be 30 ma, because th e actual voltage app lied to ring and tip is 30 v. considering the fact that the current measurement in reverse polarity mode will also become inverted, the read results must be added. the sum of both level meter results (normal- and reverse polarity) should therefore be 60 ma current difference. figure 46 shows the differential measurement method and the elimination of the offsets. figure 46 differential r esistance measurement the following calculation show s the elimination of the volt age and current offset caused by output stage and current sensor. this diff erential measurement method eliminates the offsets caused by the slic current sensor and the offset caused by the dc voltage output (ring offset voltage). duslic_0008_differentially offsets v tip/ring du di expected values measured values normal polarity reverse polarity u offset i offset i tip/ring
duslic operational description preliminary data sheet 113 ds3, 2003-07-11 differential resistance calculation: 3.8.2.10 line resistance tip/gnd and ring/gnd the duslic offers a choice of modes: either the tip- or the ring line or both can be set to high impedance by setting th e bits hir and hit in regist er bcr1 accordingly. while one of the two lines is set to high impedance, the other line is still active and able to supply a known voltage. the transversal and /or longitudinal curre nt can be measured and the line impedanc e can be calculated. because of one line (tip or ri ng) being high impeda nce, there is only current flowing in either tip or ring line. this causes the calculated current (according table 22 ) to be half the actual value. therefore, in either hir or hit mode, th e calculated current must be multiplied by a factor of two. 3.8.2.11 capacitance measurements capacitance measurements with the duslic are accomplish ed by using the integrated ramp generator function. the ramp generator is capable of applying a voltage ramp to the ring- and tip line wi th the flexibility of: ? programmable slopes from 30 v/s to 2000 v/s ? programmable start- and stop dc voltage offsets via ring offsets ? programmable start time of the voltage ra mp after enabling the level meter function figure 47 shows the voltage ramp and the voltage levels at t he ring and tip line. the slope of the ramp can be programmed (refer to cram coefficients). the ring offset voltages ro1, ro2, and ro3 might be used as start and st op voltages. the ramp starts, for instance, at ro1 and st ops at ro2. the current can be calculated as i(t) = c measure *du/dt, where du/dt is the slope and i(t) is the current that will be measured by the level meter. to ac curately measure values, the integr ation must start after the current has settled to a constant value. this can be ca lculated by the time constant of the ringer load. it is recommende d that the programmabl e ring generator delay be set higher than three times the time constant of the ringer load. when there is a resistor in parallel to the capacitor (for example, leak age), it is recommended to measure symmetrically around i measure normal () v tr prog , v offset + r ------------------------------------------------ i offset + = i measure reverse () v ? tr prog , v offset + r --------------------------------------------------- - i offset + = measure normal () i measure reverse () ? 2v tr prog , r ----------------------------------- = r 2v tr prog , i measure normal () i measure reverse () ? ------------------------------------------------------------ -------------------------------- r line r prot r stab ++ ==
duslic operational description preliminary data sheet 114 ds3, 2003-07-11 the voltage zero crossing. this can be achieved by programming the ring generator delay appropriately (see duslicos dc contro l parameter 2/4). the integration time for the current measurement is determined by the ring frequen cy (refer to cram coefficients, see table 21 ). after the integration time, measurement stops automatically only if the bit lm-once in register lmcr 1 is set. otherwise, the level meter would continuously measure the current even if the ramp is finished and turned into its constant voltage position. because of the constant voltage, no curr ent will flow. figure 47 capacitance measurement ezm14053 sli c-p sli c-e/ -e2 sli c-s/ -s2 v hr v bath gnd ( v hr + v bath )/2 tip ring ring tip programmable voltage slope v dc,start v dc,stop lmcr1: lm-en intreg2: lm-ok i ntreg2: ready int. period t ring,delay line current i settl i ng of l i ne cur r ent i : set r i nger del ay t ring,delay hi gh enough to do the actual cur r ent measur ement i n the settl ed cur r ent r ange. gnd v batr /2 v batr
duslic operational description preliminary data sheet 115 ds3, 2003-07-11 example assumptions: ? capacitance as object to be determined: c measure =9.8f ?resistor r measure in series to c measure : r measure =6930 ? ? = r measure *c measure = 67.9 ms calculating parameter values: ? choose ring offset voltage 1: ro1 = 70 v (start voltage on tip/ring where the ramp should start; programmed by ring offset voltage ro1) ? choose ring offset voltage 2: ro2 = ?30 v (e nd voltage on ti p/ring where the ramp should stop; programmed by ring offset voltage ro2) ? choose slope of ramp wh ile testing: du/dt = 200 v/s ? time from start to stop of the ramp from ro1 to ro2 is 100 v/200 v/s = 500 ms ? time from start to zero cross is 70 v/200 v/s = 350 ms ? choose integration time: t i =1/f ring = 1/100 hz = 10 ms ? measure around zero cross from 345 ms to 355 ms ?t ring,delay is programmed to 345 ms ? check ring generator delay: t ring,delay > 3* = 204 ms ok! ? expected current i = c measure *du/dt = 1.96 ma ? choose current for dc levelmet er current 50% full scale i lm,dc =2ma note: a current of 2 m a will result in lm result = 0.5 (half of the full scale value) program sequence set the following parameter values: integration time t i =1/f ring = 1/100 hz = 10 ms select the dc level meter by setting bits lm- sel[3:0] in regist er lmcr2 to 0101 execute the level meter onl y once by setting bit lm-onc e in register lmcr1 to 1. apply ring offset voltage ro1 to ring and tip line by se tting bits rng-offset[1:0] in register lmcr3 to 01. parameter symbol & value duslicos voltage slope of ramp generator du/dt = 200 v/s dc control parameter 3/4 ring frequency f ring = 100 hz dc control parameter 2/4 ring generator delay t ring,delay = 345 ms dc control parameter 2/4 ring offset voltage 1 ro1 = 7 0 v dc control parameter 2/4 ring offset voltage 2 ro2 = ? 30 v dc control parameter 2/4 dc levelmeter current 50% full scale i lm,dc = 2 ma dc control parameter 4/4
duslic operational description preliminary data sheet 116 ds3, 2003-07-11 enable the ramp generator by setting bit ramp-en in register lmcr2 to 1. apply ring offset voltage ro2 to ring and tip line by se tting bits rng-offset[1:0] in register lmcr3 to 10. enable the level meter by setting bit lm-en in regi ster lmcr1 to 1. ? comment: the voltage ramp starts at ro1 and ramps up/down until ro2 is achieved. after the integration time, the result will be stored within lmres1 and lmres2 registers. read the result regist ers lmres1 and lmres2 the actual current i cmeasure amounts to: the capacitance c measure calculates as: example: lm value = 0x3af2 = 15090 lm result =0.4605 i cmeasure = 2*2 ma*0.4605 = 1.842 ma c measure = 1,842 ma/200 v/s = 9.21 f note: to increase the accuracy an offset calibration can be performed. the voltage ramp can be applied wh en the line is set to high imp edance by setting bits hir and hit in register bcr1. in this way, th e offset currents can be measured and substracted later. as an al ternative a rising and a fa lling ramp can be used to compensate current offsets. 3.8.2.12 line capacitance measur ements ring and tip to gnd the voltage ramp can be applie d to either line, whereas th e other line is set to high impedance by setting bits hir and hit in register bcr1 accordingly. in this way, capacitance measurements from ring and ti p to gnd may be accomplished. because of one line being set to high impedance, the actual line current will be twice the calculated one (multiplication by a fa ctor of two necessary). 3.8.2.13 foreign- and ri ng voltage measurements the duslic supports two user-programmable i nput/output pins (io3 , io4) that can be used for measuring external volt ages. if the pins io3 and/or io4 are led properly over a voltage divider to the ring- an d tip wire, foreign voltages fr om external voltage sources supplied to the lines can be measured on either pin; even a differential measurement will i cmeasure 2i lm dc , lm resul t = c measure i cmeasure du dt ------- - ------------------------- =
duslic operational description preliminary data sheet 117 ds3, 2003-07-11 be supported (io4-io3). to select the input information that is to be taken for the measurement, set bits lm-sel[3:0] in configuration register lmcr2 (see table 27 ). the measurement is accomplished by the dc level meter function. figure 48 foreign voltage measurement principle figure 48 shows the connection and external re sistors used for supporting foreign voltage measurements at the ring and tip lines. since the pins io3 and io4 suppo rt analog input func tionality and are lim ited to a certain voltage range of v vcm 1.0 v (typ. 1.5 v 1.0 v), the values for the voltage divider must be determined according to following conditions: table 27 measurement input selection lm-sel[3:0] in register lmcr2 measurement input 1010 voltage on io3 1011 voltage on io4 1111 voltage io4 ? io3 duslic_0009_foreign_voltage slic slicofi-2/-2s it il acn / p dcn / p linecard ac dc foreign voltage source vcm r3 r4 vcm r2 r1 io4 io3 r prot + r stab r prot + r stab
duslic operational description preliminary data sheet 118 ds3, 2003-07-11 maximum level of the ex pected foreign voltages voltage range of io3 and io4 = v vcm 1.0 v the voltage on io3 or io4 is measured with a refere nce to vcm. hence, an input voltage of v vcm on either input pin would result into zero output value. whereas a voltage of v vcm + 1 v would result into the n egative full scale value, v vcm ? 1 v would result into the positive full scale value respectively. fo r that reason the voltage divider must be referenced to vcm. the unknown foreign voltage v foreign can be calculated as: v input =v iox ?v vcm (refer to table 22 ) v iox = voltage on pins io x (e.g. pins io3, io4) the resistor directly connected to either ring or tip (r1, r3 ) should be hi gh enough so that the loop impedance will not be affected by them. several m ? s, such as 10 m ?, would be a reasonable value. the following example illustrates the potential voltage range that can be measured by choosing the values as: r1 = r3 = 10 m ? r2 = r4 = 47 k ? the values given for the maximum and minimu m voltage levels are: v vcm =1.5v v input,max =1v v iox,max =2.5v v input,min =?1v v iox,min =0.5v the voltage range would sp an from 215 v to ?212 v. to measure small input voltag es on io3/io4 more accurate ly, the integration function may be enabled by setting bit lm-e n in register lmcr1 to 1 (see figure 40 ). to measure the ring voltage supplied to either ring or tip or even both (balanced ringing) pins via io3 and io4 , the rectifier can be enable d by setting bit lm-rect in register lmcr2 to 1. v foreign v input r1 r2 + r2 --------------------- - v vcm + = v foreign max , v input max , r1 r2 + r2 --------------------- - v vcm + 215 v == v foreign min , v input min , r1 r2 + r2 --------------------- - v vcm + ?212 v ==
duslic operational description preliminary data sheet 119 ds3, 2003-07-11 3.9 signal path and test loops the following figures show th e main ac and dc signal path and the integrated analog and digital loops of the duslic-e/-e2/-p and duslic -s/-s2. please note the interconnections between th e ac and dc pictures of the respective chip set. 3.9.1 ac test loops figure 49 ac test loops du slic-e/-e2/-p/-es/-es2 tg mu-law lin hpx1 ax1 frx lpx exp + ar1 tg hpr frr lpr th hpx2 ax2 ar2 cor8 pcm16k cox16 ac-dlb-32k cor-64 ac-dlb-128k dac adc im2 opim_4m pofi prefi opim_an ac-dlb-4m pcm16k 16k ax-dis ar-dis th-dis lprx-cr ax-dis frx-dis hpx-dis pd-ac-gn pd-ac-ad him-an pd-ac-po pd-ac-da im-dis ptg, tg1-en, tg2-en ar-dis hpr-dis frr-dis lpx-cr mu-law lin lm-ac ac-dlb-8k lm-val* cmp lm-dc lm2pcm lm -sel[3:0] lm-notch lm-filt lm-en pcm2dc hpx-dis ttx gen. ttx-12k ttx-dis + im3 + ttx adapt. ttx-12k ttx-dis pd-ttx-a + + pd-ac-pr ac-xgain itac acn/acp a b a b c programmable via cram not programmable switch switch always available available only when bit test-en = 1 *lm-val-h[7:0] lm -val-l[7:0] d im1 pcm in: receive data from pcm or iom-2 interface pcm out: transmit data to pcm or iom-2 interface duslic_0022_intstru_slicofi2_a
duslic operational description preliminary data sheet 120 ds3, 2003-07-11 figure 50 ac test loops duslic-s/-s2/-se/-se2 duslic_0023_intstru_slicofi2s_c tg mu-law lin hpx1 ax1 frx lpx exp + ar1 tg hpr frr lpr th hpx2 ax2 ar2 cor8 cox16 ac-dlb-32k cor-64 16k ax-dis ar-dis th-dis lprx-cr ax-dis frx-dis hpx-dis ptg, tg1-en, tg2-en ar-dis hpr-dis frr-dis lpx-cr pcm2dc hpx-dis a b c pcm in: receive data from pcm or iom-2 interface ac-dlb-128k dac adc im2 opim_4m pofi prefi opim_an ac-dlb-4m pd-ac-gn pd-ac-ad him-an pd-ac-po pd-ac-da im-dis ttx gen. ttx-12k ttx-dis + im3 + ttx adapt. ttx-12k ttx-dis pd-ttx-a + + pd-ac-pr ac-xgain itac acn/acp a b programmable via cram not programmable switch switch always available available only when bit test-en = 1 im1 lm-ac ac-dlb-8k lm-val* lm-dc lm2pcm lm-sel[3:0] lm-notch lm-filt lm-en *lm-val-h[7:0] lm-val-l[7:0] d mu-law lin cmp pcm out: transmit data to pcm or iom-2 interface
duslic operational description preliminary data sheet 121 ds3, 2003-07-11 3.9.2 dc test loops figure 51 dc test loops duslic duslic_0022_intstru_slicofi2_b pd-dc-ad dc prefi dc adc pd-dc-pr it il io3 io4 io4 ? io3 vdd offset lp dc-hold ramp-en ramp + hook lm-dc ro1 ro1 dc char. rg ro1 + + lm-en lm-rect rtr-sel rng-offset[1:0] pcm2dc dcn/dcp c programmable via cram not programmable pd-dc-da pd-dcbuf pc-pofi-hi dc pofi dc buf dc dac lm-sel[3:0] switch switch always available available only when bit test-en = 1 it pd-ofhk offhook comp il pd-gnkc gnk comp c1 pd-hvi hv-int. c2 overt. comp pd-ovtc d *offset-h[7:0] offset-l[7:0] offset*
duslic interfaces preliminary data sheet 122 ds3, 2003-07-11 4interfaces the duslic offers two diff erent interfaces to conne ct to a digi tal network: pcm interface combined with a serial microcontroller interface iom-2 interface. the pcm/iom-2 pin selects the interface mode. ? pcm/iom-2 = 0: iom-2 mode. ? pcm/iom-2 =1: pcm/ c mode. the analog tip/ring interface connec ts the duslic to the subscriber. 4.1 pcm interface with a seri al microcontroller interface in pcm/ c interface mode, voice and contro l data are separate d and handled by different pins of the slicofi-2x . voice data are transferre d via the pcm highways while control data are transferred usin g the microcontroller interface. 4.1.1 pcm interface the serial pcm interface is used to transfer a-law or -law-compressed voice data. in test mode, the pcm interface c an also transfer linear data. the eight signals of the pcm interface are used as fo llows (two pcm highways): the fsc pulse identifies the be ginning of a receive and tran smit frame for both channels (see figure 52 ). the pclk clock sig nal synchronizes the data transfer on the dxa (dxb) and dra (drb) lines. on all channels, bytes are serialized with the msb first. as a default setting, the rising edge indicates the start of the bit, while the falling edge is used to buffer the contents of the received data on dra (drb). if double clock rate is selected (pclk clock rate is tw ice the data ra te), the first rising edge indicates the start of a bit, while, by default, the second fallin g edge is used to buffe r the contents of the data line dra (drb). pclk: pcm clock, 128 khz to 8192 khz fsc: frame synchronization clock, 8 khz dra: receive data input for pcm highway a drb: receive data input for pcm highway b dxa: transmit data outp ut for pcm highway a dxb: transmit data outp ut for pcm highway b tca : transmit control output for pcm highway a. active low during transmission tcb : transmit control output for pcm highway b. active low during transmission
duslic interfaces preliminary data sheet 123 ds3, 2003-07-11 figure 52 general pcm interface timing the data rate of the interface can vary from 2*128 kbit/s to 2*8192 kbit/s (two highways). a frame may consist of up to 128 time slot s of 8 bits each. the time slot and pcm highway assignment for ea ch duslic channel can be programmed. receive and transmit time slots can also be programmed individually. ezm14046 fsc pclk dra dxa 125 s tca detail a 0 12 31 3 high 'z' high 'z' fsc pclk dra dxa tca high 'z' high 'z' voice data voice data 0 1 72 3 4 5 6 01 7 23456 bit clock time slot time slot detail a:
duslic interfaces preliminary data sheet 124 ds3, 2003-07-11 when duslic is transmitting data on dxa (dxb), pin tca (tcb ) is activated to control an external driving device. the dra/b and dxa/b pins may be connected to form a bidire ctional data pin for special purposes, such as for the serial interface port (sip) with th e subscriber line data (sld) bus. the sld approach prov ides a common interface for analog or digital per-line components. for more de tails, please see the ics for communications 1) user?s manual available on request from infineon technologies. table 28 shows pcm interface examples; other frequencies are also possible (such as 1536 khz). 1) ordering no. b115-h6377- x-x-7600, published by infineon technologies. table 28 slicofi-2x pcm interface configuration clock rate pclk [khz] single/double clock [1/2] time slots [per highway] data rate [kbit/s per highway] 128 1 2 128 256 2 2 128 256 1 4 256 512 2 4 256 512 1 8 512 768 2 6 384 768 1 12 768 1024 2 8 512 1024 1 16 1024 2048 2 16 1024 2048 1 32 2048 4096 2 32 2048 4096 1 64 4096 8192 2 64 4096 8192 1 128 8192 f 1 f/64 f f 2 f/128 f/2 valid pclk clock rates are: f =n 64 khz (2 n 128)
duslic interfaces preliminary data sheet 125 ds3, 2003-07-11 figure 53 setting the slopes in register pcmc1 fsc pclk pclk bit 7 time-slot 0 receive slope transmit slope 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 dbl- clk x- slope r- slope no- drive shift pcmo[2:0] dbl- clk x- slope r- slope no- drive shift pcmo[2:0] dbl- clk x- slope r- slope no- drive shift pcmo[2:0] dbl- clk x- slope r- slope no- drive shift pcmo[2:0] dbl- clk x- slope r- slope no- drive shift pcmo[2:0] dbl- clk x- slope r- slope no- drive shift pcmo[2:0] dbl- clk x- slope r- slope no- drive shift pcmo[2:0] dbl- clk x- slope r- slope no- drive shift pcmo[2:0] single clock mode double clock mode pcmc1: pcmc1: ezm22011
duslic interfaces preliminary data sheet 126 ds3, 2003-07-11 4.1.2 control of the active pcm channels the slicofi-2x offers additional f unctionality on the pc m interface including three-party conferencing and a 16 khz sample rate. five configuration bits and the pcm configuration registers control the activation of the pcm tran smit channels. for details of the different functions see chapter 5.2 . table 29 gives an overview of the data transmission configurat ion of the pcm channels. x1l is used only when linear data are transmitted. in this case, the time slot for x1 is defined by the number x1 -ts from the pcmx1 register. the time slot for x1l is defined by the number x1-ts + 1. note: pcm means pcm- coded data (a-law/ -law) hb1 and hb2, and lb1 and lb 2 indicate the high byte and low byte of linearly transmitted data for an 8 khz (16 khz) sample rate. note: modes in rows with gray bac kground are for testing purposes only. table 29 active pcm chan nel configuration bits control bits transmit pcm channel pcmx- en conf- en confx- en pcm16k lin x1 x1l x2 x3 x4 0 0 0 ? ? ????? 1 0 0 0 0 pcm???? 100 0 1hblb??? 010 ? ???pcmpcm? 1 1 0 0 0 pcm ? pcm pcm ? 1 1 0 0 1 hb lb pcm pcm ? 0 0 1 ? ? ? ? pcm pcm pcm 1 0 1 0 0 pcm ? pcm pcm pcm 1 0 1 0 1 hb lb pcm pcm pcm 0 1 1 ? ? ? ? pcm pcm pcm 1 1 1 0 0 pcm ? pcm pcm pcm 1 1 1 0 1 hb lb pcm pcm pcm 1?? 1 0ds1??ds2? 1 ? ? 1 1 hb1 ? lb1 hb2 lb2
duslic interfaces preliminary data sheet 127 ds3, 2003-07-11 4.1.3 serial microcontroller interface the microcontroller interface consists of four lines: cs , dclk, din and dout. there are two different command types. reset commands have just one byte. read/write commands have two command bytes wi th the address offset information located in the second byte. a write command (see figure 54 ) consists of two command bytes and the following data bytes. the first command by te determines whether the command is read or write, how the command field is to be us ed, and which duslic channel (a or b) is written. the second command byte cont ains the address offset. a read command (see figure 55 ) consists of two command bytes written to din. after the second command byte is ap plied to din, a dump-byte co nsisting of 1s is written to dout. data transfer star ts with the first byte following the ?dump-byte?. cs: a synchronization sign al starting a read or write access to slicofi-2x . dclk: a clock signal (up to 8.192 mhz) supplied to slicofi-2x . din: data input carries data from the master device to the slicofi-2x . dout: data output carries data from slicofi-2x to a master device.
duslic interfaces preliminary data sheet 128 ds3, 2003-07-11 figure 54 serial microcontro ller interface write access note: serial microcontr oller interfaces write access shown in figure 54 is for n data bytes and single byte commands. figure 55 serial microcontro ller interface read access comm 1st dclk din cs comm 2nd data data data data byte 1 data byte n comm 1st din cs n data bytes write command single byte write command ezm14057 comm 1st dclk din dout cs comm 2nd 'dump byte' data data data data byte 1 data byte n * high impedance * * ezm14058
duslic interfaces preliminary data sheet 129 ds3, 2003-07-11 programming the microcontro ller interface without clocks at fsc, mclk, pclk the slicofi-2x can also be programmed via the c interface without any clocks connected to the fsc, mclk, an d pclk pins. this can be us eful in power down modes when additional power sa vings at the system level is necess ary. in this case, a data clock of up to 1.024 mhz ca n be used on pin dclk. because the slicofi-2x exits the basic reset routine on ly if clocks at the fsc, mclk, and pclk pins are applied, it is not possible to program the slicofi-2x without any clocks at these pins directly after the hardware reset or power on reset. note: it is necessary to first ex it the basic reset ro utine with the clocks applied in oder to get the system running. 4.2 the iom-2 interface iom-2 defines an industry-s tandard serial bus for inte rconnecting telecommunication ics for a broad range of application s ? typically isdn-based applications. the iom-2 bus provides a symmetrical full-dup lex communication link containing data, control/programming and st atus channels. providing data, control, and status information via a serial cha nnel reduces the pin count and cost by simplifying the line card layout. the iom-2 interface consists of two data lines and tw o clock lines as follows: slicofi-2x handles data as describ ed in the iom-2 sp ecification for analog devices. this specification is available on request from infineon technologies. du: data upstream carries data from the slicofi-2x to a master device. dd: data downstream ca rries data from the master device to the slicofi-2x . fsc: a frame synchronization signal (8 khz) supplied to slicofi-2x . dcl: a data clock signal (204 8 khz or 4096 khz) supplied to slicofi-2x .
duslic interfaces preliminary data sheet 130 ds3, 2003-07-11 figure 56 iom-2 i/f timing for up to 16 voice channels (per 8 khz frame) the information is multiplexed into frames th at are transmitted at an 8 khz rate. the frames are subdivided into eight sub-frames (see figure 56 ), with one sub-frame dedicated to each transceiver or pair of codecs (in this case, each sub-frame is dedicated to two slicofi-2x channels). the sub-frames provide channels for data, programming, and status in formation for a si ngle transceiver or codec pair. figure 57 and figure 58 show iom-2 interfac e timings for the two possible data clock (dcl) signal frequencies: 125 s voice channel a voice channel a voice channel b voice channel b fsc dcl dd du detail a ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 detail a dd du monitor channel monitor channel c/i channel c/i channel mr mx mr mx ezm04104
duslic interfaces preliminary data sheet 131 ds3, 2003-07-11 figure 57 iom-2 interface timing (d cl = 4096 khz, per 8 khz frame) figure 58 iom-2 interface timing (d cl = 2048 khz, per 8 khz frame) both duslic channels (see figure 56 ) can be assigned to one of the eight time slots. set the iom-2 time slot selection as shown in table 30 by pin-strapping. in this way, up to 16 channels can be handled with one iom-2 interfac e on the linecard. fsc dcl dd du 4096 khz detail b detail b fsc dcl bit n bit 0 bit 1 dd/du 125 s ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ezm04105 fsc dcl dd du 2048 khz detail c detail c fsc dcl bit n bit 0 bit 1 dd/du 125 s ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 ezm04106
duslic interfaces preliminary data sheet 132 ds3, 2003-07-11 2 mhz or 4 mhz dcl is se lected by the sel24 pin: sel24 = 0: dcl = 2048 khz sel24 = 1: dcl = 4096 khz table 30 iom-2 time slot assignment ts2 ts1 ts0 iom-2 operating mode 0 0 0 0 0 0 1 1 0 1 0 1 time slot 0; dcl = 2048, 4096 khz time slot 1; dcl = 2048, 4096 khz time slot 2; dcl = 2048, 4096 khz time slot 3; dcl = 2048, 4096 khz 1 1 1 1 0 0 1 1 0 1 0 1 time slot 4; dcl = 2048, 4096 khz time slot 5; dcl = 2048, 4096 khz time slot 6; dcl = 2048, 4096 khz time slot 7; dcl = 2048, 4096 khz
duslic interfaces preliminary data sheet 133 ds3, 2003-07-11 4.2.1 iom - 2 interface monitor transfer protocol monitor channel operation the monitor channel is used for the transf er of maintenance in formation between two functional blocks. using two monitor control bits (mr and mx) per di rection, the data is transferred in a complete hands hake procedure. the mr and mx bits in the fourth byte (c/i channel) of the iom-2 fr ame are used for the handshak e procedure of the monitor channel. the monitor channel transmission oper ates on a pseudo- asynchronous basis: data transfer (in bits) on the bus is synchronized to frame sync fsc. data flow (in bytes) is asynchronously controlled by the handshake procedure. for example: data is placed onto the dd-moni tor-channel by the m onitor transmitter of the master device (bit dd-mx is activated: se t to 0). this data tr ansfer will be repeated within each frame (125 s rate) until it is acknowledged by the slicofi-2x monitor receiver by setting the bit du-mr to 0, which is checked by the moni tor transmitter of the master device. the data rate on io m-2 monitor channels is 4 kbits/s. figure 59 iom - 2 interface monitor transfer protocol ezm04125 monitor transmitter monitor receiver monitor receiver monitor transmitter master device slicofi-2x mx mr mx mx mx mr mr mr dd du
duslic interfaces preliminary data sheet 134 ds3, 2003-07-11 monitor handshake procedure the monitor channel wo rks in three states a start of a transmission is initiated by a monitor transmitte r in sending out an active mx bit together with the first byte of data (t he address of the receiv er) to be transmitted in the monitor channel. the monitor channel remains in this st ate until the addresse d monitor receiver acknowledges the receiv ed data by sending out an acti ve mr bit, which means that the data transmission is repeated each 125 s frame (minimum is one repetition). at this time, the monitor transmitte r evaluates the mr bit. flow control can only take pl ace when the transmitter?s mx an d the receiver?s mr bit are in active state. because the receiver is capab le of receiving th e monitor data at least twice (in two consecutive frames), it is able to check for data e rrors. if two different bytes are received, the receiver will wait for the receipt of two identical successi ve bytes (last look function). a collision resolution mechanism (checks if another device is trying to se nd data at the same time) is implemented in th e transmitter. this is done by looking for the inactive (1) phase of the mx bit and making a per-bit collision check on the transmitted monitor data (check if there are transmitte d 1s on du/dd line; du/dd li ne are open-drain lines). any abort leads to a reset of the slicofi-2x command stack, the device is ready to receive new commands. to maximize speed during data transfers, the transmitter anticipates the falling edge of the receiver?s acknowledgment. due to the programming struct ure, duplex operation is no t possible. sending any data to the slicofi-2x while transmission is active is not allowed. data transfer to the slicofi-2x starts with a slicofi-2x -specific address byte (81 h ). attention: each byte on the monitor channe l must be sent at least twice according to the iom-2 monito r handshake procedure. idle state: a pair of inacti ve (set to 1) mr and mx bits during two or more consecutive frames: en d of message (eom) sending state: mx bit is activa ted (set to 0) by the monito r transmitter, together with data bytes (can be chan ged) on the mo nitor channel acknowledging: mr bit is set to active (set to 0) by th e monitor receiver, together with a data byte remaining in the monitor channel.
duslic interfaces preliminary data sheet 135 ds3, 2003-07-11 figure 60 state diagram of the slicofi-2x monitor transmitter mr ? mr bit received on dd line mx ? mx bit calculated and expected on du line mxr ? mx bit sampled on du line cls ? collision within the moni tor data byte on du line rqt ? request for transmissi on form internal source abt ? abort request/indication idle mx = 1 abort mx = 1 wait mx = 1 1 st byte mx = 0 eom mx = 1 n th byte ack mx = 1 wait for ack mx = 0 mr rqt mr mxr mr + mxr mxr mr mxr initial state mr rqt mr mr mr rqt mr mr rqt mr rqt mr cls/abt any state
duslic interfaces preliminary data sheet 136 ds3, 2003-07-11 figure 61 state diagram of the slicofi-2x monitor receiver mr ? mr bit calculated and transmitted on du line mx ? mx bit received data downstream (dd line) ll ? last look of monitor by te received on dd line abt ? abort indication to internal source ezm04127 idle mr = 1 1 st byte rec. mr = 0 abort mr = 1 byte valid mr = 0 new byte mr = 1 n th byte rec. mr = 1 wait for ll mr = 0 initial state mx mx abt any state mx mx ll mx mx ll mx ll mx mx mx mx ll mx ll wait for ll mr = 0 mx mx mx ll
duslic interfaces preliminary data sheet 137 ds3, 2003-07-11 address byte messages to and from the slicofi-2x start with the following byte: 4.2.2 slicofi-2x identification command for the iom-2 interface only, a two-byte ident ification command is defined for analog line iom-2 devices to unambiguous ly identify different devices by software. a device requesting the identification of the slicofi-2x will send the foll owing two byte code: each device will then respon d with its specific iden tification co de. for the slicofi-2x , this two byte identification code is: 4.2.3 operation with iom-2 te devices (1.536 mhz) the duslic can be oper ated either in pcm/ c mode or iom-2 mode . in case of iom-2 mode the duslic supports th e standard iom-2 data clock rates of 4.096 mhz (double clock) or 2.048 mhz (single clock). some applications however require the iom-2 te mode wh ich uses a clock rate of 1.536 mhz and a data rate of 768 kbit/s, respectively. as the iom-2 mode of the duslic doesn t support a clock rate of 1.536 mhz, the pcm/ c mode is used: it is possible to operate the duslic in pcm/ c mode at 1.536 mhz and to connect its pcm inte rface directly to the iom-2 interface of the host device as shown in figure 62 . bit 76543210 10000001 10000000 00000000 10000000 10000101
duslic interfaces preliminary data sheet 138 ds3, 2003-07-11 figure 62 pcm/mc mode used for iom-2 te interface at 1.536 mhz as shown in figure 62 the slicofi-2x is operated in pcm/ c mode. the controlling is done via the serial c interface by a microcontroller, whereas the voice data is mapped from the pcm output of the slicofi-2x to the iom-2 interface and vice versa. special care has to be taken about the time sl ot counting: in th e example shown in figure 62 , the pcm timeslot ts5 corresponds to the b2 channel of iom channel 1. the slicofi-2x has to be programmed for pcm do uble clock rate (bit dbl-clk in register pcm1). the pcm time slot (rece ive and transmit) can be programmed with register pcmr1 and pcmx1. as the dxa/b output of the slicofi-2x is only active in the sele cted time slot and is high impedance in other time slot s, the pcm output of the slicofi-2x can be directly connected to the iom-2 bus with out any additional hardware (provided that the driving capability of the slicofi-2x is strong enough for the con nected iom-2 bus). slicofi-2x pcm/c mode controller serial controller interface other iom-2 device 1.536 mhz mode iom-2 interface 1.536 mhz dclk fsc 8 khz mclk dclk/1.536 mhz dd/768 kbit/s du/768 kbit/s fsc pclk dra or drb dxa or dxb fsc dclk du dd ts0 high imp. iom channel 0 fsc slicofi-2x dxa or dxb iom-2 du ts6 high imp. ts4 high imp. ts3 high imp. ts2 high imp. ts1 high imp. ts10 high imp. ts9 high imp. ts8 high imp. ts7 high imp. ts11 high imp. b1 b2 m c/i iom channel 0 b1 b2 m c/i iom channel 0 b1 b2 m c/i iom channel 2 b1 b2 m c/i b1 b2 m c/i iom channel 1 b1 b2 m c/i selclk vdd pcm/iom-2 ts5 active ts0 iom channel 0 slicofi-2x dra or drb iom-2 dd ts6 ts4 ts3 ts2 ts1 ts10 ts9 ts8 ts7 ts11 b1 b2 m c/i iom channel 0 b1 b2 m c/i iom channel 0 b1 b2 m c/i iom channel 2 b1 b2 m c/i b1 b2 m c/i iom channel 1 b1 b2 m c/i ts5 iom1536_768kbits_mod e
duslic interfaces preliminary data sheet 139 ds3, 2003-07-11 it has also to be considered that the slicofi-2x offers 3.3 v logic levels for the pcm voice data. if the driv ing capability or the 3.3 v level of the slicofi-2x are not sufficient, an external driver/levelsh ifter has to be used. the slicofi-2x offers appropriate signals for controlling an ex ternal bus driver. 4.3 tip/ring interface the tip/ring interface is the interface that connects the subscrib er to the duslic. it meets itu-t recommendation q.552 fo r z interface and applicable lssgr. for the performance of the tip/ring interface, see chapter 6.1 and chapter 6.2 ; for application circuits, see chapter 7 .
duslic slicofi-2x command st ructure and programming preliminary data sheet 140 ds3, 2003-07-11 5 slicofi-2x command structure and programming with the commands described in this chapter, the slicofi-2x can be programmed, configured, and tested very fl exibly via the microcontrolle r interface or via the iom-2 interface monitor channel. the command structure uses one-byte and two-byte commands to ensure a highly flexible an d quick programming procedure for the most common commands. structure of the first command byte the first command byte includes the r/w bit, the addresses of th e different channels, and the command type. bit 76543210 rd op adr[2:0] cmd[2:0] rd read data rd = 0 write data to chip. rd = 1 read data from chip. op selects the usage of the cmd field op = 0 the cmd field works as a co mmand/indication operation (ciop) command and acts like the m[2:0] bits located in the cidd byte of the iom interface. see table 31 . op = 1 the cmd field acts as the sop, cop, or pop co mmand described below (microcontroller interface mode only). . bit 76543210 0 0 adr[2:0] m2 m1 m0
duslic slicofi-2x command st ructure and programming preliminary data sheet 141 ds3, 2003-07-11 table 31 m2, m1, m0: genera l operating mode command/indication operation (ciop) slicofi-2x operating mode (for details see ?overview of all duslic operating modes? on page 74 ) m2 m1 m0 1 1 1 sleep, power down (pdrx) 0 0 0 power down high impedance (pdh) 0 10any active mode 1 0 1 ringing (actr burst on) 1 1 0 active with metering 1 00ground start 0 01ring pause adr[2:0] channel address for the subsequent data adr[2:0] = 0 0 0 channel a adr[2:0] = 0 0 1 channel b (other codes reserv ed for future use) cmd[2:0] command for programming the slicofi-2x (op = 1) or command equivalent to the cidd chann el bits m[2:0] in microc ontroller interface mode (op = 0) the first four commands have no se cond command byte following. all necessary in formation is present in the first command byte. cmd[2:0] = 0 0 0 soft reset of the chip (reset routine for all channels will reset all configuration regi sters, cram data is not affected). cmd[2:0] = 0 0 1 soft rese t for the specified channel a or b in adr field cmd[2:0] = 0 1 0 resychroniz ation of the pcm interface (only available when pin pcm/iom-2 =1) cmd[2:0] = 0 1 1 reser ved for future use the second four commands are followed by a seco nd command byte that defines additional informati on, such as specifying sub-addresses of the cram. cmd[2:0] = 1 0 0 sop command (sta tus operation; pr ogramming, and monitoring of all status-relevant data). cmd[2:0] = 1 0 1 cop command (coeff icient operation; programming, and monitoring of all coefficients in the cram).
duslic slicofi-2x command st ructure and programming preliminary data sheet 142 ds3, 2003-07-11 structure of the second command byte the second command byte specifies a pa rticular sop, cop, or pop command, depending on the cmd[2:0] bits of the first command byte. in the following sections, the contents of this register are described for ea ch command group. the second command byte specifies the initial of fset for the subsequent data bytes. after each data byte is transferred, the internal offset is incremented au tomatically. therefore, it is possible to send a varied number of data bytes with on e sop, cop, or pop command. writing over read-only regist ers will not destroy their contents. register description example at the beginning of each register descripti on, a single line gi ves information about: offset: offset of register address (hex) name: short name of the register detailed name: detailed name of the register reset value: value of the register after reset (hex) ?hw? ? value depends on specific hardware fuses test status: ?t? ? the register has no effect unless the test-en bit in register lmcr1 is set to 1 channel selection: ?n? ? the register affects both slicofi-2x channels, ?y? ? the register affects a specific slicofi-2x channel the line is organized as follows (with example): cmd[2:0] = 1 1 0 pop command (signal processing operation programming). cmd[2:0] = 1 1 1 reserve d for production tests offset name detailed name reset value test per channel 27 h tstr1 test register 1 00 h ty
duslic slicofi-2x command st ructure and programming preliminary data sheet 143 ds3, 2003-07-11 5.1 overview of commands sop status operation cop coefficient operation pop pop operation (only slicofi-2 peb 3265 used for duslic-e/-e2/-p) bit76543210 byte 1 rd 1 adr[2:0] 1 0 0 byte 2 offset[7:0] bit76543210 byte 1 rd 1 adr[2:0] 1 0 1 byte 2 offset[7:0] bit76543210 byte 1 rd 1 adr[2:0] 1 1 0 byte 2 offset[7:0]
duslic preliminary data sheet 144 ds3, 2003-07-11 5.2 slicofi-2 command structure and programming this section describes only the sl icofi-2 peb 3265 command structure and programming. 5.2.1 sop command the status operation (sop) co mmand provides access to the configuration and status registers of the slicofi-2. common register s change the mode of the entire slicofi-2 chip. all other register s are channel-specific. it is possi ble to access si ngle or multiple registers. multiple register access is achieved by an auto matic offset increment. write access to read-only registers is ignored and does not abort th e command sequence. offsets may change in future versions of the slicofi-2. attention: to ensure proper functionality, it is essenti al that all unused register bits have to be filled with zeros. 5.2.1.1 sop register overview 00 h revision revision number (read-only) rev[7:0] 01 h chipid 1 chip identification 1 (read-only) for internal use only 02 h chipid 2 chip identification 2 (read-only) for internal use only 03 h chipid 3 chip identification 3 (read-only) for internal use only 04 h fuse1 fuse register 1 for internal use only 05 h pcmc1 pcm configuration register 1 dbl-clk x-slope r-slope no-drive-0 shift pcmo[2:0]
duslic preliminary data sheet 145 ds3, 2003-07-11 06 h xcr extended configuration register edsp-en asynch-r 0 0 0 0 07 h intreg1 interrupt register 1 (read-only) int-ch hook gndk gnkp icon vtrlim otemp sync-fail 08 h intreg2 interrupt register 2 (read-only) lm-thres ready rstat lm-ok io[4:1]-du 09 h intreg3 interrupt register 3 (read-only) dtmf-ok dtmf-key[4:0 ] utdr-ok utdx-ok 0a h intreg4 interrupt register 4 (read-only) edsp-fail 0 0 0 cis-bof cis-buf cis-req cis-act 0b h chkr1 checksum register 1 (high byte) (read-only) sum-ok chksum-h[6:0] 0c h chkr2 checksum register 2 (low byte) (read-only) chksum-l[7:0] 0d h lmres1 level metering result 1 (high byte) (read-only) lm-val-h[7:0] 0e h lmres2 level metering result 2 (low byte) (read-only) lm-val-l[7:0] 0f h fuse2 fuse register 2 for internal use only 10 h fuse3 fuse register 3 for internal use only
duslic preliminary data sheet 146 ds3, 2003-07-11 11 h mask mask register ready-m hook-m gndk-m gnkp-m ic on-m vtrlim-m otemp-m sync-m 12 h ioctl1 i/o control register 1 io[4:1]-inen io[4:1]-m 13 h ioctl2 i/o control register 2 io[4:1]-oen io[4:1]-dd 14 h ioctl3 i/o control register 3 dup[3:0] dup-io[3:0] 15 h bcr1 basic configuration register 1 hir hit sleep-en revpol actr actl sel-slic[1:0] 16 h bcr2 basic configuration register 2 rext-en soft-dis ttx-dis ttx-12k him-an ac-xgain utdx-src pdot-dis 17 h bcr3 basic configuration register 3 mu-law lin pcm16k pcmx-en confx-en conf-en lprx-cr cram-en 18 h bcr4 basic configuration register 4 th-dis im-dis ax-dis ar-dis frx-dis frr-dis hpx-dis hpr-dis 19 h bcr5 basic configuration register 5 -en utdx-en cis-auto cis-en lec-out lec-en dtmf-src dtmf-en 1a h dscr dtmf sender configuration register dg-key[3:0] cor8 ptg tg2-en tg1-en 1b h reserved 00000000
duslic preliminary data sheet 147 ds3, 2003-07-11 1c h lmcr1 level metering configuration register 1 test-en lm-en lm-thm pcm2dc lm2 pcm lm-once lm-mask dc-ad16 1d h lmcr2 level metering configuration register 2 lm-notch lm-filt lm-rect ramp-en lm-sel[3:0] 1e h lmcr3 level metering configuration register 3 ac-short- en rtr-sel lm-itime[3:0 ] rng-offset[1:0] 1f h ofr1 offset register 1 (high byte) offset-h[7:0] 20 h ofr2 offset register 2 (low byte) offset-l[7:0] 21 h pcmr1 pcm receive register 1 r1-hw r1-ts[6:0] 22 h pcmr2 pcm receive register 2 r2-hw r2-ts[6:0] 23 h pcmr3 pcm receive register 3 r3-hw r3-ts[6:0] 24 h pcmr4 pcm receive register 4 r4-hw r4-ts[6:0] 25 h pcmx1 pcm transmit register 1 x1-hw x1-ts[6:0]
duslic preliminary data sheet 148 ds3, 2003-07-11 26 h pcmx2 pcm transmit register 2 x2-hw x2-ts[6:0] 27 h pcmx3 pcm transmit register 3 x3-hw x3-ts[6:0] 28 h pcmx4 pcm transmit register 4 x4-hw x4-ts[6:0] 29 h tstr1 test register 1 pd-ac-pr pd-ac-po pd-ac-ad pd-ac-da pd-ac-gn pd-gnkc pd-ofhc pd-ovtc 2a h tstr2 test register 2 pd-dc-pr 0 pd-dc-ad pd-dc-da pd-dcbuf 0 pd-ttx-a pd-hvi 2b h tstr3 test register 3 0 0 ac-dlb-4m ac-dlb- 128k ac-dlb- 32k ac-dlb- 8k 00 2c h tstr4 test register 4 opim-an opim-4m cor-64 cox-16 0 0 0 0 2d h tstr5 test register 5 0 0 0 dc-pofi- hi dc-hold 0 0 0
duslic preliminary data sheet 149 ds3, 2003-07-11 5.2.1.2 sop register description 00 h revision revision number (read-only) curr. rev. n bit 76543210 rev[7:0] rev[7:0] current revision numb er of the slicofi-2. 01 h chipid 1 chip identificati on 1 (read-only) hw n bit765 4 3210 for internal use only 02 h chipid 2 chip identificati on 2 (read-only) hw n bit765 4 3210 for internal use only 03 h chipid 3 chip identificati on 3 (read-only) hw n bit765 4 3210 for internal use only 04 h fuse1 fuse register 1 hw n bit765 4 3210 for internal use only
duslic preliminary data sheet 150 ds3, 2003-07-11 05 h pcmc1 pcm configuration register 1 00 h n bit 7 6 5 4 3 2 1 0 dbl-clk x-slope r-slope no-drive-0 shift pcmo[2:0] dbl-clk clock mode for the pcm interface (see figure 53 on page 125 ) dbl-clk = 0 single-clocking is used. dbl-clk = 1 double-clocking is used. x-slope transmit slope (see figure 53 on page 125 ) x-slope = 0 transmission starts wi th rising edge of the clock. x-slope = 1 transmission starts wi th falling edge of the clock. r-slope receive slope (see figure 53 on page 125 ) r-slope = 0 data is sampled with falling edge of the clock. r-slope =1 data is sampled with ri sing edge of the clock. no- drive-0 driving mode for bit 0 (only avai lable in single -clocking mode). no-drive = 0 bit 0 is driven the entire clock period. no-drive = 1 bit 0 is driven during the first half of the clock period only. shift shifts the access edge s by one clock cycle in double-clocking mode. shift = 0 no shift takes place. shift = 1 shift takes place. pcmo[2:0] all pcm timing is moved by pcmo da ta periods against the fsc signal. pcmo[2:0] = 0 0 0 no offset is added. pcmo[2:0] =0 0 1 one data period is added. pcmo[2:0] = 1 1 1 seven data periods are added.
duslic preliminary data sheet 151 ds3, 2003-07-11 06 h xcr extended configuration register 00 h n bit765 43210 edsp- en async h-r 000 0 edsp-en enables the enhanced digita l signal processor edsp. edsp-en = 0 enhanced digital sign al processor is switched off. edsp-en = 1 enhanced digital sign al processor is switched on. asynch-r enables asynchronous ringi ng in case of intern al or external ringing. asynch-r = 0 internal or external ringing with zero crossing selected. asynch-r = 1 asynchronous ringing selected. note: when internal ring ing is used, the ringing signal can be turned of f without waiting for zero crossing.
duslic preliminary data sheet 152 ds3, 2003-07-11 07 h intreg1 interrupt register 1 (read-only) 80 h y bit 76543210 int-ch hook gndk gnkp icon vtrlim otemp sync- fail int-ch interrupt channel bit. th is bit indicates that the correspond ing channel caused the last interrupt. will be automa tically set to zero after all interrupt registers were read. int-ch = 0 no interrupt in corresponding channel. int-ch = 1 interrupt caused by corresponding channel. hook indicates on-hook or off-hook for the loop in all operating modes (via the itx pin); filtered by the dup (data upstream persistence) counter and interrupt generation masked by the hook-m bit. indicates ground st art in case of ground start mode is selected. a change of this bit generates an interrupt. hook = 0 on-hook. hook = 1 off-hook detected. gndk indicates ground key information in all active modes via the il pin; filtered for ac suppression by the dup counte r and interrupt g eneration masked by the gndk-m bit. a change of this bit generates an interrupt. gndk = 0 no ground key indicated. gndk = 1 ground key indication; lo ngitudinal current (threshold 17 ma) detected. gnkp ground key polarity. indicati ng the active ground key level (positive/negative) inte rrupt generation masked by the gnkp-m bit. a change of this bit generates an interrupt. this bit can be used to obtain information about interf erence voltage influence. gnkp = 0 negative ground ke y threshold level active. gnkp = 1 positive ground ke y threshold level active.
duslic preliminary data sheet 153 ds3, 2003-07-11 icon constant current information. filter ed by dup-io counter and interrupt generation masked by the icon-m bit. a change of this bit generates an interrupt. icon = 0 resistive or co nstant voltage feeding. icon = 1 constant current feeding. vtrlim exceeding of a programmed voltage threshold for the tip/ring voltage, filtered by the dup-io counter and interrupt generation masked by the vtrlim-m bit. a change of th is bit causes an interrupt. the voltage threshold for the tip/ring voltage is set in cram (calculated with duslicos dc control para meter 2/4: tip-ring threshold). vtrlim = 0 voltage at tip/ ring is below the limit. vtrlim = 1 voltage at tip/ ring is above the limit. otemp thermal overload warning from the slic-e/-e2/-p line drivers masked by the otemp-m bit. an interrupt is only generated if the otemp bit changes from 0 to1. otemp = 0 temperature at slic -e/-e2/-p is below the limit. otemp = 1 temperature at slic -e/-e2/-p is above the limit. in case of bit pdot-dis = 0 (register bcr2) the duslic is switched automati cally into pdh mode and otemp is hold at 1 until th e slicofi-2 is set to pdh by a ciop/cidd command. sync-fail failure of the synchronization of the iom-2/pcm interface. an interrupt is only generated if the sync-fa il bit changes from 0 to1. resynchronization of the pcm interface can be done with the resynchronization command (see chapter 5 ) sync-fail = 0 synchronization ok. sync-fail = 1 synchro nization failure.
duslic preliminary data sheet 154 ds3, 2003-07-11 after a hardware reset, the rstat bit is se t and generates an in terrupt. therefore the default value of intreg2 is 20 h . after reading all four inte rrupt registers, the intreg2 value changes to 4f h . 08 h intreg2 interrupt register 2 (read-only) 20 h y bit 76543210 lm- thres ready rstat lm-ok io[4:1]-du lm-thres indication whether the le vel metering result is above or below the threshold set by the cram coefficients lm-thres = 0 level metering result is below threshold. lm-thres = 1 level metering result is above threshold. ready indication whether the ramp generator has finished. an interrupt is only generated if the ready bi t changes from 0 to 1. upon a new start of the ramp generator, the bit is set to 0. for further information regarding soft reversal see chapter 2.7.2.1 . ready = 0 ramp generator active. ready = 1 ramp generator not active. rstat hardware reset status since last interrupt. rstat = 0 no hardware reset has o ccurred since the last interrupt. rstat = 1 hardware reset has occu rred since the last interrupt. lm-ok level metering sequence has finished. an interrupt is only generated if the lm-ok bit changes from 0 to 1. lm-ok = 0 level meteri ng result not ready. lm-ok = 1 level mete ring result ready. io[4:1]-du data on i/o pins 1 to 4 filtered by dup-io counter and interrupt generation masked by the io[4:1]-du-m bits. a cha nge of any of this bits generates an interrupt.
duslic preliminary data sheet 155 ds3, 2003-07-11 09 h intreg3 interrupt register 3 (read-only) 00 h y bit 76543210 dtmf- ok dtmf-key[4:0] utdr- ok utdx- ok dtmf-ok indication of a valid dtmf key by the dtmf receiv er. a change of this bit generates an interrupt. dtmf-ok = 0 no valid dtmf ke y was encountered by the dtmf receiver. dtmf-ok = 1 a valid dtmf key was encountered by the dtmf receiver. dtmf-key[4:0] valid dtmf keys decoded by the dtmf receiver. table 32 valid dtmf ke ys (bit dtmf-key4 = 1) f low [hz] f high [hz] digit dtmf- key4 dtmf- key3 dtmf- key2 dtmf- key1 dtmf- key0 6971209110001 6971336210010 6971477310011 7701209410100 7701336510101 7701477610110 8521209710111 8521336811000 8521477911001 9411336011010 9411209* 11011 9411477#11100 6971633a11101 7701633b11110
duslic preliminary data sheet 156 ds3, 2003-07-11 8521633c11111 9411633d10000 utdr-ok universal tone detection receiv e (such as fax/modem tones) utdr-ok = 0 no specific tone signal was detected. utdr-ok = 1 a specific to ne signal was detected. utdx-ok universal tone detection transmi t (such as fax/modem tones) utdx-ok = 0 no specific tone signal was detected. utdx-ok = 1 a specific to ne signal was detected. table 32 valid dtmf ke ys (bit dtmf-key4 = 1) (cont?d) f low [hz] f high [hz] digit dtmf- key4 dtmf- key3 dtmf- key2 dtmf- key1 dtmf- key0
duslic preliminary data sheet 157 ds3, 2003-07-11 0a h intreg4 interrupt register 4 (read-only) 00 h y bit 76543210 edsp- fail 000cis- bof cis- buf cis- req cis- act edsp-fail indication of a malfunction of th e enhanced digital signal processor edsp. edsp-fail = 0 enhanced digital signal processo r edsp normal operation. edsp-fail = 1 enhanced digital sig nal processor edsp failure. it is necessary to restart this d sp with bit edsp-en in the xcr register set. cis-bof caller id buffer overflow. an interrupt is only generated if the cis-bof bit changes from 0 to 1. cis-bof = 0 not data buffer overflow has occurred. cis-bof = 1 too many bytes have been written to the data buffer for caller id generation. caller id generation is aborted and the buffer is cleared. cis-buf caller id buffer underflow. an interru pt is only generated if the cis-buf bit changes from 0 to 1. cis-buf = 0 data buffer for call er id generati on is filled. cis-buf = 1 data buffer for call er id generation is empty (underflow).
duslic preliminary data sheet 158 ds3, 2003-07-11 cis-req caller id data request . an interrupt is only gener ated if the cis-req bit changes from 0 to 1. cis-req = 0 caller id data buffer reques ts no data. cis-req = 1 caller id data buffer requests more data to transmit, when the amount of data stored in the buffer is less than the buffer request size. cis-act caller id generator active. this is a status bit only. no interrupt will be generated. cis-act = 0 caller id g enerator is not active. cis-act = 1 caller id generator is active.
duslic preliminary data sheet 159 ds3, 2003-07-11 0b h chkr1 checksum register 1 (high byte) (read-only) 00 h y bit 76543210 sum- ok chksum-h[6:0] sum-ok information about the va lidity of the checksu m. the checksum is valid if the intern al checksum calculat ion is finished. checksum calculation: for (cram_adr = 0 to 159) do cram_dat = cram[cram_adr] csum[14:0] = (csum[13:0] & 1) ?0?) xor (?0000000? & cram_dat[7:0]) xor (?0000000000000? & csu m[14] & csum[14]) end 1) ?&? means a concatenation ; not the logic operation sum-ok = 0 cram che cksum is not valid. sum-ok = 1 cram checksum is valid. chksum-h[6:0] cram checksum high byte 0c h chkr2 checksum register 2 (low byte) (read-only) 00 h y bit 76543210 chksum-l[7:0] chksum-l[7:0] cram checksum low byte
duslic preliminary data sheet 160 ds3, 2003-07-11 0d h lmres1 level metering result 1 (high byte) (read-only) 00 h y bit76543210 lm-val-h[7:0] lm-val-h[7:0] lm result high byte (selected by the lm-sel bi ts in the lmcr2 register) 0e h lmres2 level metering resu lt 2 (low byte) (read-only) 00 h y bit 76543210 lm-val-l[7:0] lm-val-l[7:0] lm result low byte (selected by the lm-sel bi ts in the lmcr2 register) 0f h fuse2 fuse register 2 hw y bit 76543210 for internal use only 10 h fuse3 fuse register 3 hw y bit 76543210 for internal use only
duslic preliminary data sheet 161 ds3, 2003-07-11 the mask bits in the mask register only infl uence the generation of an interrupt. even if the mask bit is set to 1, the corresponding status bit in th e intregx regist ers is updated to show the current status of the corresponding event. 11 h mask mask register ff h y bit 76543210 ready -m hook -m gndk -m gnkp -m icon -m vtrlim -m otemp -m sync -m ready-m mask bit for ramp generator ready bit ready-m = 0 an interrupt is generated if the ready bit changes from 0 to 1. ready-m = 1 changes of the ready bit do not generate interrupts. hook-m mask bit for off-hook detection hook bit hook-m = 0 each change of the ho ok bit generate s an interrupt. hook-m = 1 changes of the hook bi t do not generate interrupts. gndk-m mask bit for ground ke y detection gndk bit gndk-m = 0 each change of the gn dk bit generate s an interrupt. gndk-m = 1 changes of the gndk bi t do not generate interrupts. gnkp-m mask bit for ground key level gnkp bit gnkp-m = 0 each change of the gnkp bit generates an interrupt. gnkp-m = 1 changes of the gnkp bit do not generate interrupts. icon-m mask bit for constant curr ent information icon bit icon-m = 0 each change of the ic on bit generates an interrupt. icon-m = 1 changes of the icon bi t do not generate interrupts. vtrlim-m mask bit for programmed vo ltage limit vtrlim bit vtrlim-m = 0 each change of the vtrlim bit g enerates an interrupt. vtrlim-m = 1 changes of the vtrlim bit do not generate interrupts.
duslic preliminary data sheet 162 ds3, 2003-07-11 otemp-m mask bit for thermal overload warning otemp bit otemp-m = 0 a change of the otem p bit from 0 to 1 generates an interrupt. otemp-m = 1 a change of the ot emp bit from 0 to 1 does not generate interrupts. sync-m mask bit for synchronization failure sync-fail bit sync-m = 0 a change of the sync-fail bit from 0 to 1 generates an interrupt. sync-m = 1 a change of the sync-fail bit fr om 0 to 1 does not generate interrupts.
duslic preliminary data sheet 163 ds3, 2003-07-11 the mask bits io[4:1]-m only influence the generation of an interrupt. even if the mask bit is set to 1, the correspo nding status bit in the intreg x registers is updated to show the current status of the corresponding event. 12 h ioctl1 i/o control register 1 0f h y bit 76543210 io[4:1]-inen io[4:1]-m io4-inen input enable for prog rammable i/o pin io4 io4-inen = 0 input schmitt trig ger of pin io4 is disabled. io4-inen = 1 input schmitt trig ger of pin io4 is enabled. io3-inen input enable for prog rammable i/o pin io3 io3-inen = 0 input schmitt trig ger of pin io3 is disabled. io3-inen = 1 input schmitt trig ger of pin io3 is enabled. io2-inen input enable for prog rammable i/o pin io2 io2-inen = 0 input schmitt trig ger of pin io2 is disabled. io2-inen = 1 input schmitt trig ger of pin io2 is enabled. io1-inen input enable for prog rammable i/o pin io1 io1-inen = 0 input schmitt trig ger of pin io1 is disabled. io1-inen = 1 input schmitt trig ger of pin io1 is enabled. io4-m mask bit for io4-du bit io4-m = 0 each change of the io 4 bit generates an interrupt. io4-m = 1 changes of the io4 bi t do not generate interrupts. io3-m mask bit for io3-du bit io3-m = 0 each change of the io 3 bit generates an interrupt. io3-m = 1 changes of the io3 bi t do not generate interrupts.
duslic preliminary data sheet 164 ds3, 2003-07-11 io2-m mask bit for io2-du bit io2-m = 0 each change of the io 2 bit generates an interrupt. io2-m = 1 changes of the io2 bi t do not generate interrupts. io1-m mask bit for io1-du bit io1-m = 0 each change of the io 1 bit generates an interrupt. io1-m = 1 changes of the io1 bi t do not generate interrupts.
duslic preliminary data sheet 165 ds3, 2003-07-11 13 h ioctl2 i/o control register 2 00 h y bit 76543210 io[4:1]-oen io[4:1]-dd io4-oen enabling output driver of the io4 pin io4-oen = 0 the output driver of the io4 pin is disabled. io4-oen = 1 the output driver of the io4 pi n is enabled. io3-oen enabling output driver of the io3 pin io3-oen = 0 the output driver of the io3 pin is disabled. io3-oen = 1 the output driver of the io3 pi n is enabled. io2-oen enabling output driver of the io2 pin. if slic-p is selected (bits sel-slic [1:0] in register bcr1 set to 01), pin io2 cannot be controlled by the user but is utilized by the slicofi-2 to control the c3 input of slic-p. io2-oen = 0 the output driver of the io2 pin is disabled. io2-oen = 1 the output driver of the io2 pi n is enabled. io1-oen enabling output driver of the io1 pin. if external ringing is selected (bit r ext-en in register bcr2 set to 1), pin io1 cannot be controlled by the user but is utilized by the slicofi-2 to control the ring relay. io1-oen = 0 the output driver of the io1 pin is disabled. io1-oen = 1 the output driver of the io1 pi n is enabled. io4-dd value for the programmable i/o pin io4 if programmed as an output pin. io4-dd = 0 the corresponding pin is driving a logic 0. io4-dd = 1 the corresponding pin is driving a logic 1. io3-dd value for the programmable i/o pin io3 if programmed as an output pin. io3-dd = 0 the corresponding pin is driving a logic 0. io3-dd = 1 the corresponding pin is driving a logic 1.
duslic preliminary data sheet 166 ds3, 2003-07-11 io2-dd value for the programmable i/o pin io2 if programmed as an output pin. io2-dd = 0 the corresponding pin is driving a logic 0. io2-dd = 1 the corresponding pin is driving a logic 1. io1-dd value for the programmable i/o pin io1 if programmed as an output pin. io1-dd = 0 the corresponding pin is driving a logic 0. io1-dd = 1 the corresponding pin is driving a logic 1. 14 h ioctl3 i/o control register 3 94 h y bit 765 43210 dup[3:0] dup-io[3:0] dup[3:0] data upstream persistence counte r end value. restricts the rate of interrupts generated by the hook bit in the interrupt register intreg1. the interval is programmable from 1 to 16 ms in steps of 1 ms (reset value is 10 ms). the dup[3:0] valu e affects the blocking period for ground key detection (see chapter 2.6 ). dup-io[3:0] data upstream persistenc e counter end value for the i/o pins when used as digital input pins. the bits icon and vtrlim in register intreg1. the interval is programmable from 0.5 to 60.5 ms in steps of 4 ms (reset value is 16.5 ms). dup[3:0] hook active, ringing hook power down gndk gndk f min,acsup 1) 1) minimum frequency for ac suppression. 0000 1 2 ms 4 ms 125 hz 0001 2 4 ms 8 ms 62.5 hz ... 1111 16 32 ms 64 ms 7.8125 hz
duslic preliminary data sheet 167 ds3, 2003-07-11 15 h bcr1 basic configuration register 1 00 h y bit 7 6 5 4 3210 hir hit sleep- en revpol actr actl sel-slic[1:0] hir this bit modifies different basic mo des. in ringing mode, an unbalanced ringing on the ring wire (ror) is enabled. in acti ve mode, high impedance on the ring wire is activa ted (hir). if the hit bit is set in addition to the hir bit, the hirt mode is activated. hir = 0 normal operation (ringing mode). hir = 1 controls slic-e/-e2/-p inte rface and sets the ring wire to high impedance (active mode). hit this bit modifies different basic mode s. in ringing mode, an unbalanced ringing on the tip wire (rot) is ena bled. in active mo de, high impedance on the tip wire is perform ed (hit). if the hir bit is set in addition to the hit bit, the hirt mo de is activated. hit = 0 normal operat ion (ringing mode). hit = 1 controls slic-e/-e2/-p inte rface and sets the tip wire to high impedance (active mode). sleep-en enables sleep mode of th e duslic channel. valid only in the power down mode of the slicofi-2. sleep-en = 0 sleep mode is disabled. sleep-en = 1 sleep mode is enabled. note: sleep-en has to be set before entering the power down mode. revpol reverses the polarity of dc feeding revpol = 0 normal polarity. revpol = 1 reverse polarity.
duslic preliminary data sheet 168 ds3, 2003-07-11 actr selection of extended battery feedin g in active mode. also changes the voltage in power down resistive mode for slic-p. in this case, v batr for slic-p and v hr ? v bath for slic-e/-e2 is used. actr = 0 no extended batt ery feeding selected. actr = 1 extended batt ery feeding selected. actl selection of the low ba ttery supply voltage v batl on slic-e/-e2/-p if available. valid only in the ac tive mode of the slicofi-2. actl = 0 low battery supply vo ltage on slic-e/-e2/-p is not selected. actl = 1 low battery supply volt age on slic-e/-e2/-p is selected. sel-slic[1:0] selection of the current slic type used. for sl ic-e/-e2 and slic-p, the appropriate predefined mode table has to be selected. sel-slic[1:0] = 0 0 slic-e/-e2 selected. sel-slic[1:0] = 0 1 slic-p selected. sel-slic[1:0] = 1 0 slic-p selected for extremely power sensitive applications. sel-slic[1:0] = 1 1 reserved for future use.
duslic preliminary data sheet 169 ds3, 2003-07-11 for slic-p two sele ctions are possible. the standard slic-p selection automatically uses the io2 pin of the slicofi-2 to control the c3 pi n of the slic-p. by using pin c3 as well as the pins c1 and c2, all possible operati ng modes of the slic-p v1.1 can be selected. for slic-p v1.2 only the operating modes with 90 ma current limita tion can be selected (actl90, acth90, actr90). note: if with slic-p v1.2 the 60 ma current limitation modes (actl60, acth60, actr60) ar e to be used, then the slic type sel-slic[1:0] = 10 has to be programmed. in this case the c3 pin of the slic-p v1.2 can al so be controlled by the io2 pin of the slicofi-2. however, the io2 pin has then to be programmed manually by the user according to the slic-p v1.2 interface code table. for extremely power sensitive appl ications using external ringing with slic-p sel-slic[1:0] = 10 shou ld be chosen. in this case, internal unbalanced ringing is not needed and therefore there is no need to switch the c3 pi n of the slic-p to 'hi gh'. the c3 pin of the slic-p must be connected to gnd and the io2 pin of the slicofi-2 is programmable by the user. there is no need for a high battery voltage fo r ringing either. this mode uses v batr for the on-hook voltage (e.g. ?48 v) in power down resistive (pdr) mode and t he other battery supply voltages (e.g. v bath = ?24 v and v batl = ?18 v) can be used for the off-hook state. this wi ll help to save po wer because the lowest possible battery voltage can be se lected (see duslic voltage and power application note).
duslic preliminary data sheet 170 ds3, 2003-07-11 16 h bcr2 basic configuration register 2 00 h y bit 76543210 rext- en soft- dis ttx- dis ttx- 12k him-an ac- xgain utdx- src pdot- dis rext-en enables the use of an ex ternal ring signal generat or. synchronization is done via the rsync pin an d the ring burs t enable signal is transferred via the io1 pin. rext-en = 0 external ringing is disabled. rext-en = 1 external ringing enabled. soft-dis polarity soft reversal (to mi nimize noise on dc feeding) soft-dis = 0 polarity so ft reversal active. soft-dis = 1 polarity hard reversal. ttx-dis disables the generation of ttx bursts for metering signals. if ttx bursts are disabled, reverse polar ity will be used instead. ttx-dis = 0 ttx bursts are enabled. ttx-dis = 1 ttx bursts are dis abled, reverse polarity used. ttx-12k selection of ttx frequencies ttx-12k = 0 selects 16 khz ttx si gnals instead of 12 khz signals. ttx-12k = 1 12 khz ttx signals. him-an higher impedance in analog impedance matching loop. the value of this bit must correspo nd to the select ion done in the duslicos tool when calcul ating the coefficients. if the coefficients are calculated with standard impedance in analog impedance matching loop, him-an must be set to 0; if the coefficients are calculated with high impedance in analog impedance matching loop, him-an must be set to 1. him-an = 0 standard impedance in analog impedance matching loop him-an = 1 high impedance in an alog impedance matching loop
duslic preliminary data sheet 171 ds3, 2003-07-11 ac-xgain analog gain in transmit dire ction (should be set to zero). ac-xgain = 0 no addit ional analog gai n in transmit direction. ac-xgain = 1 additional 6 db anal og amplification in transmit direction. utdx-src universal tone detect or transmit source. any change of bit utdx-src only becomes effective, if bit utdx-en in register bcr5 is c hanged from 0 to 1. utdx-src utdx-sum lec-en signal source for utdx 0 0 don?t care transmit 0 0 don?t care transmit 0 1 0 receive + transmit 0 1 1 receive + transmit 1 don?t care 0 transmit 1 don?t care 0 transmit 1 don?t care 1 lec-output 1 don?t care 1 lec-output (see figure 29 on page 56 )
duslic preliminary data sheet 172 ds3, 2003-07-11 pdot-dis power down overtemperature disable pdot-dis = 0 when overtemperatur e is detected, the slic is automatically switched into power down high impedance mode (pdh). this is the safe operation mode for the slic-e/- e2/-p in case of overtemperature. to leave the automatically activated pdh mode, dusl ic must be switched manually to pdh mo de and then in the mode as desired (otherwise the ot emp bit in in treg1 will not change ba ck to 0). pdot-dis = 1 when overtemp erature is detected, the slic-e/-e2/-p does not au tomatically switch into power down high impedance mode. in this case, the output current of the slic-e /-e2/-p buffers is limited to a value that keeps the slic-e/-e2/-p temperature below the upper te mperature limit. the otemp bit in intreg1 changes back to 0 if the slic temperature is bel ow the threshold again. the int registers may be locked in addition if otemp-m = 0. note: transients on tip/ ring can cause false overtemperature alarms, because the otemp signal is not d eglitched. to avoi d this situation it is recommended to sw itch off the automatic power down on overtemperature (pdot-dis = 1) and integrat e a function for overtemperature handl ing in the interrupt service routine.
duslic preliminary data sheet 173 ds3, 2003-07-11 17 h bcr3 basic configuration register 3 00 h y bit 76 5 43210 mu- law lin pcm16k pcmx- en confx -en conf- en lprx- cr cram- en mu-law selects the pcm law mu-law = 0 a-l aw enabled. mu-law = 1 -law enabled. lin voice transmission in a 16-bit linea r representation for test purposes. note: voice transmission on the other channel is inhibited if one channel is set to linear m ode and the iom-2-interface is used. in the pcm/microcontroller interface mode, both channels can be in linear mode using two consecutiv e pcm timeslots on the highways. a proper timeslot select ion must be specified. lin = 0 pcm mode enabled (8 bit, a-law or -law). lin = 1 linear mode enabled (16 bit). pcm16k selects 16-khz sample ra te for the pcm interface. pcm16k = 0 16-khz mode disa bled (8 khz sampling rate). pcm16k = 1 16-khz mode enabled. pcmx-en enables writing of subscriber voice data to the pcm highway. pcmx-en = 0 writing of subscriber voice data to pcm highway is disabled. pcmx-en = 1 writing of subscriber voice data to pcm highway is enabled. confx-en enables an external three-party conference. confx-en = 0 external c onference is disabled. confx-en = 1 external conference is enabled.
duslic preliminary data sheet 174 ds3, 2003-07-11 conf-en selection of three-party conferencing for this channel. the voice data of this channel and the voice data fr om the corresponding conferencing channels (see chapter 4.1.1 ) are added and fed to analog output (see chapter 2.10 ). conf-en = 0 three-party conferencing is not selected. conf-en = 1 three-party conferencing is selected. lprx-cr select cram coefficients for the filter characteristic of the lpr/lpx filters. these coefficients may be enabled in case of a modem transmission to improve modem performance. lprx-cr = 0 coefficients from rom are used. lprx-cr = 1 coefficients from cram are used. cram-en coefficients from cram are used fo r programmable filters and dc loop behavior. cram-en = 0 coefficients from rom are used. cram-en = 1 coefficients from cram are used.
duslic preliminary data sheet 175 ds3, 2003-07-11 18 h bcr4 basic configuration register 4 00 h y bit 76543210 th-dis im-dis ax-dis ar-dis frx- dis frr- dis hpx- dis hpr- dis th-dis disables the th filter. th-dis = 0 th filter is enabled. th-dis = 1 th filt er is disabled (h th = 0). im-dis disables the im filter. im-dis = 0 im filter is enabled. im-dis = 1 im filter is disabled (h im = 0). ax-dis disables the ax filter. ax-dis = 0 ax filt er is enabled. ax-dis = 1 ax filter is disabled (h ax = 1). ar-dis disables the ar filter. ax-dis = 0 ar filter is enabled. ax-dis = 1 ar filter is disabled (h ar = 1). frx-dis disables the frx filter. frx-dis = 0 frx filter is enabled. frx-dis = 1 frx filter is disabled (h frx = 1). frr-dis disables the frr filter. frr-dis = 0 frr filter is enabled. frr-dis = 1 frr filter is disabled (h frr = 1). hpx-dis disables the high-pass filt er in transmit direction. hpx-dis = 0 high-pass filter is enabled. hpx-dis = 1 high-pass fi lter is disabled (h hpx = 1).
duslic preliminary data sheet 176 ds3, 2003-07-11 hpr-dis disables the high-pass filt er in receive direction. hpr-dis = 0 high-pass filter is enabled. hpr-dis = 1 high-pass filter is disabled (h hpr = 1).
duslic preliminary data sheet 177 ds3, 2003-07-11 19 h bcr5 basic configuration register 5 00 h y bit 76543210 utdr- en utdx- en cis- auto cis-en lec- out lec-en dtmf- src dtmf- en utdr-en enables the universal tone de tection in receive direction. utdr-en = 0 universal tone detection is disabled. utdr-en = 1 universal to ne detection is enabled. utdx-en enables the universal tone de tection in transmit direction. utdx-en = 0 universal tone detection is disabled. utdx-en = 1 universal to ne detection is enabled. cis-auto controls the turn-off behavio r of the caller id sender. cis-auto = 0 the caller id sender st ops when cis-en is switched to 0. cis-auto = 1 the caller id sender continues sending data until the data buffer is empty. cis-en enables the caller id s ender in the slicofi-2. note: the caller id sender is config ured directly by programming the according pop registers. caller id data are written to a 48 byte ram buffer. according to the buffer request size, this influences the cis-req and cis-buf bits. cis-en = 0 caller id sender is disa bled and caller id data buffer is cleared after all data are sent or if cis-auto = 0. cis-en = 1 caller id sender is e nabled and caller id data can be written to the data buffer. afte r the last data bit is sent, stop bits are sent to the subscriber. caller id data are sent to th e subscriber when the number of bytes written to the buffer exceeds cis-brs + 2.
duslic preliminary data sheet 178 ds3, 2003-07-11 lec-out line echo cancellation result for transmit path. lec-out = 0 line echo cancellati on result used for dtmf only. lec-out = 1 line echo cancellati on result fed to transmit path. lec-en line echo cancellation lec-en = 0 line echo cancel lation for dtmf disabled. lec-en = 1 line echo canc ellation for dt mf enabled. dtmf-src selects data source for dtmf receiver. any change of bit dtmf-s rc only becomes effective, if bit dtmf-en is changed from 0 to 1. dtmf-src = 0 the transmit path data (with or without lec) is used for the dtmf detection. dtmf-src = 1 the receive path data is used for the dtmf detection. dtmf-en enables the dtmf receiver of the sl icofi-2. the dtmf receiver will be configured properly by progr amming registers in the edsp. dtmf-en = 0 dtmf receiver is disabled. dtmf-en = 1 dtmf receiver is enabled.
duslic preliminary data sheet 179 ds3, 2003-07-11 1a h dscr dtmf sender configuration register 00 h y bit 76543210 dg-key[3:0] cor8 ptg tg2-en tg1-en dg-key[3:0] selects one of sixteen dtmf ke ys generated by the two tone generators. the key will be genera ted if tg1-en and tg2-en are 1. table 33 dtmf keys f low [hz] f high [hz] digit dg-key3 dg -key2 dg-key1 dg-key0 697120910001 697133620010 697147730011 770120940100 770133650101 770147760110 852120970111 852133681000 852147791001 941133601010 941 1209 * 1 0 1 1 9411477#1100 697 1633 a 1 1 0 1 770 1633 b 1 1 1 0 852 1633 c 1 1 1 1 941 1633 d 0 0 0 0 cor8 cuts off receive path at 8 khz be fore the tone ge nerator summation point. allows sending of tone generator si gnals with no overlaid voice. cor8 = 0 cut off rece ive path disabled. cor8 = 1 cut off re ceive path enabled.
duslic preliminary data sheet 180 ds3, 2003-07-11 ptg programmable coefficients for to ne generators will be used. ptg = 0 frequencies set by dg -key are used fo r both tone generators. tone generator tg1 level: ?5 dbm0 tone generator tg2 level: ?3 dbm0 ptg = 1 cram coefficients used for both tone generators. tone generator tg1 and tg 2 frequencies and levels can be programmed in th e duslicos dc control parameters 3/4. the levels are set in dbm0: level[dbm] = level[dbm0] + l r [dbr] tg2-en enables tone generator two tg2-en = 0 tone gene rator is disabled. tg2-en = 1 tone gene rator is enabled. tg1-en enables tone generator one tg1-en = 0 tone generator is disabled. tg1-en = 1 tone gene rator is enabled. 1b h reserved 00 h y bit 76543210 00000000
duslic preliminary data sheet 181 ds3, 2003-07-11 1c h lmcr1 level metering config uration register 1 22 h y bit 7 6 5 4 3 2 1 0 test- en lm-en lm- thm pcm2dc lm2 pcm lm- once lm- mask dc- ad16 test-en activates the slicofi-2 test features controlled by test registers tstr1 to tstr5. test-en = 0 slicofi-2 test features are disabled. test-en = 1 slicofi-2 test features are enabled. note: the test register bits can be programmed before the test-en bit is set to 1. lm-en enables level metering. a positive transitio n of this bit starts level metering (ac and dc). lm-en = 0 level metering stops. lm-en = 1 level metering enabled. lm-thm level metering threshold mask bit lm-thm = 0 a change of the lm -thres bit (register intreg2) generates an interrupt. lm-thm = 1 no interrupt is generated. pcm2dc pcm voice channel data added to the dc-output. pcm2dc = 0 no rmal operation. pcm2dc = 1 pcm voice channel data is added to dc output. lm2pcm level metering source/result (dependi ng on lm-en bit) feeding to pcm or iom-2 interface. lm2pcm = 0 normal operation. lm2pcm = 1 level metering so urce/result is fed to the pcm or iom-2 interface.
duslic preliminary data sheet 182 ds3, 2003-07-11 lm-once level metering execution mode. lm-once = 0 level metering is executed continuously. lm-once = 1 level metering is exec uted only once. to start the level meter again, the lm-e n bit must again be set from 0 to 1. lm-mask interrupt masking for level metering. lm-mask = 0 an interrupt is g enerated after level metering. lm-mask = 1 no interrupt is generated. dc-ad16 additional digital amplif ication in the dc ad path for level metering. dc-ad16 = 0 additional gain factor 16 disabled. dc-ad16 = 1 additional ga in factor 16 enabled.
duslic preliminary data sheet 183 ds3, 2003-07-11 1d h lmcr2 level metering config uration register 2 00 h y bit 76543210 lm- notch lm- filt lm- rect ramp- en lm-sel[3:0] lm-notch selection of a notch filt er instead of the band -pass filter for level metering. lm-notch = 0 notch filter selected. lm-notch = 1 band-pa ss filter selected. lm-filt enabling of a programm able band-pass or notch filter for level metering. lm-filt = 0 normal operation. lm-filt = 1 band-pass/ notch filter enabled. lm-rect rectifier in dc level meter lm-rect = 0 rectifier disabled. lm-rect = 1 rectifier enabled. ramp-en the ramp generator wor ks together with the rng-offset bits in lmcr3 and the lm-en bit to create di fferent voltage slopes in the dc- path. ramp-en = 0 ramp generator disabled. ramp-en = 1 ramp generator enabled. lm-sel[3:0] selection of the source for the level metering. lm-sel[3:0] = 0 0 0 0 ac level metering in transmit lm-sel[3:0] = 0 0 0 1 real part of ttx (ttx real ) lm-sel[3:0] = 0 0 1 0 imaginary part of ttx (ttx img ) lm-sel[3:0] = 0 0 1 1 not used lm-sel[3:0] = 0 1 0 0 dc out voltage on dcn-dcp lm-sel[3:0] = 0 1 0 1 dc current on it lm-sel[3:0] = 0 1 1 0 ac level metering in receive
duslic preliminary data sheet 184 ds3, 2003-07-11 lm-sel[3:0] = 0 1 1 1 ac level me tering in receive and transmit lm-sel[3:0] = 1 0 0 0 not used lm-sel[3:0] = 1 0 0 1 dc current on il lm-sel[3:0] = 1 0 1 0 voltage on io3 lm-sel[3:0] = 1 0 1 1 voltage on io4 lm-sel[3:0] = 1 1 0 0 not used lm-sel[3:0] = 1 1 0 1 v dd lm-sel[3:0] = 1 1 1 0 offset of dc-p refi (short circuit on dc-prefi input) lm-sel[3:0] = 1 1 1 1 voltage on io4 ? io3
duslic preliminary data sheet 185 ds3, 2003-07-11 1e h lmcr3 level metering config uration register 3 00 h y bit 76543210 ac- short -en rtr- sel lm-itime[3:0] rng- offset[1:0] ac-short-en the input pin itac will be set to a lower input impedan ce so that the capacitor c itac can be recharged faster during a soft reversal which makes it more silent during conversation. ac-short-en = 0 input impedance of the itac pin is standard. ac-short-en = 1 input impedance of the itac pin is lowered. rtr-sel ring trip method selection. rtr-sel = 0 ring trip with a dc offset is selected. rtr-sel = 1 ac ring trip is selected. recommended for short lines only. lm-itime[3:0] integration time for ac level metering. lm-itime[3:0] = 0 0 0 0 16 ms lm-itime[3:0] = 0 0 0 1 2 16 ms lm-itime[3:0] = 0 0 1 0 3 16 ms ? lm-itime[3:0] = 1 1 1 1 16 16 ms rng- offset[1:0] selection of the ri ng offset source.
duslic preliminary data sheet 186 ds3, 2003-07-11 by setting the ramp-en bit to 1, the ramp generator is star ted by setting lm-en from 0 to 1 (see figure 63 ). exception: transition of rng-offset from 10 to 11 or 11 to 10 where the ramp generator is started automatically (see figure 63 ). for ring offset ro1, the usual ?hook threshol d ring? is used. using ring offset ro2 or ro3 in any ringing mode (r inging and ring paus e) also changes t he hook thresholds. in this case the ?hook message waiting? threshold is used automatically. when using the ring offsets ro2 and ro3 for message wa iting, an additional lamp current is expected. in this case, the hook message waiting threshold should be programmed higher than the hook threshold ring. rng- offset[1:0] ring offset voltage in given mode active acth actl active ring actr ring pause ringing 0 0 voltage given by dc regulation voltage given by dc regulation ring offset ro1 hook threshold ring 0 1 ring offset ro1/2 (no dc regulation) ring offset ro1 (no dc regulation) ring offset ro1 hook threshold ring 1 0 ring offset ro2/2 (no dc regulation) ring offset ro2 (no dc regulation) ring offset ro2 hook message waiting 1 1 ring offset ro3/2 (no dc regulation) ring offset ro3 (no dc regulation) ring offset ro3 hook message waiting
duslic preliminary data sheet 187 ds3, 2003-07-11 figure 63 example for switching betw een different ring offset voltages the three programmable ring off sets are typically used fo r the following purposes: besides the typical usage described in table 34 , the ring offsets ro1, ro2, and ro3 can also be used for the generation of different custom waveforms (see figure 63 ). table 34 typical usage for the three ring offsets ring offset voltage application ring offset ro1 ringing ring offset ro2 low volta ge for message waiting lamp ring offset ro3 high volt age for message waiting lamp 10 11 rng-offset[1:0] ramp-en (register lmcr2) lm-en (register lmcr1) generated ring offset (ro) voltage t ro1 = 20 v ro2 = 40 v ro3 = 120 v 01 01 ezm35002
duslic preliminary data sheet 188 ds3, 2003-07-11 1f h ofr1 offset register 1 (high byte) 00 h y bit 76543210 offset-h[7:0] offset-h[7:0] offset register high byte. 20 h ofr2 offset register 2 (low byte) 00 h y bit76543210 offset-l[7:0] offset-l[7:0] offset register low byte. the value of this regist er together with off set-h is added to the input of the dc loop to compensate for a given offset of the current sensors in the slic-e/-e2/-p.
duslic preliminary data sheet 189 ds3, 2003-07-11 this register is not applicab le and is not used in iom-2 mode. it is only enabled in pcm/microcontroller mode. 21 h pcmr1 pcm receive register 1 00 h y bit 76543210 r1- hw r1-ts[6:0] r1-hw selection of the pcm high way for receiving pcm data or the higher byte of the first data sample if a li near 16-khz pcm mode is selected. r1-hw = 0 pcm highway a is selected. r1-hw = 1 pcm highway b is selected. r1-ts[6:0] selection of the pcm timeslot used for data reception. note: the programmed pcm timeslot mu st correspond to the available slots defined by the pc lk frequency. no recept ion will occur if a slot outside the actual numbers of slots is programmed. in linear mode (bit lin = 1 in register bcr3 ), r1-ts defines the first of two consecutive slots used for reception.
duslic preliminary data sheet 190 ds3, 2003-07-11 this register is not applicab le and is not used in iom-2 mode. it is only enabled in pcm/microcontroller mode. 22 h pcmr2 pcm receive register 2 00 h y bit 76543210 r2- hw r2-ts[6:0] r2-hw selection of the pcm highway for receiving conferencing data for conference channel b or t he lower byte of the first data sample if a linear 16-khz pcm mode is selected. r2-hw = 0 pcm highway a is selected. r2-hw = 1 pcm highway b is selected. r2-ts[6:0] selection of the pcm timesl ot used for receiving data (see description of pcmr1 register).
duslic preliminary data sheet 191 ds3, 2003-07-11 this register is not applicab le and is not used in iom-2 mode. it is only enabled in pcm/microcontroller mode. 23 h pcmr3 pcm receive register 3 00 h y bit 76543210 r3- hw r3-ts[6:0] r3-hw selection of the pcm highway for receiving conferen cing data for conference channel c or the higher byte of the se cond data sample if a linear 16-khz pcm mode is selected. r3-hw = 0 pcm highway a is selected. r3-hw = 1 pcm highway b is selected. r3-ts[6:0] selection of the pcm timesl ot used for receiving data (see description of pcmr1 register).
duslic preliminary data sheet 192 ds3, 2003-07-11 this register is not applicab le and is not used in iom-2 mode. it is only enabled in pcm/microcontroller mode. 24 h pcmr4 pcm receive register 4 00 h y bit 76543210 r4- hw r4-ts[6:0] r4-hw selection of the pcm highway for receiving conferen cing data for conference channel d or the lower byte of the second data sample if a linear 16-khz pcm mode is selected. r4-hw = 0 pcm highway a is selected. r4-hw = 1 pcm highway b is selected. r4-ts[6:0] selection of the pcm timesl ot used for receiving data (see description of pcmr1 register).
duslic preliminary data sheet 193 ds3, 2003-07-11 this register is not applicab le and is not used in iom-2 mode. it is only enabled in pcm/microcontroller mode. 25 h pcmx1 pcm transmit register 1 00 h y bit 76543210 x1- hw x1-ts[6:0] x1-hw selection of the pcm hi ghway for transmitting pc m data or the higher byte of the first data sample if a linear 16-khz pcm mode is selected. x1-hw = 0 pcm highwa y a is selected. x1-hw = 1 pcm highwa y b is selected. x1-ts[6:0] selection of the pcm timeslot used for data transmission. note: the programmed pcm timeslot mu st correspond to the available slots defined by the pc lk frequency. no transmission will occur if a slot outside the actual numbers of slots is prog rammed. in linear mode x1-ts defines the first of two consecutive slots used for transmission. pcm data transmission is controlled by the bits 6 through 2 in register bcr3.
duslic preliminary data sheet 194 ds3, 2003-07-11 this register is not applicab le and is not used in iom-2 mode. it is only enabled in pcm/microcontroller mode. 26 h pcmx2 pcm transmit register 2 00 h y bit 76543210 x2- hw x2-ts[6:0] x2-hw selection of the pcm hi ghway for transmitting conferencing data for conference channel c + s or c + d or the lower byte of the first data sample if a linear 16-k hz pcm mode is selected. x2-hw = 0 pcm highwa y a is selected. x2-hw = 1 pcm highwa y b is selected. x2-ts[6:0] selection of the pcm timeslot used for transmitting data (see description of pcmx1 register).
duslic preliminary data sheet 195 ds3, 2003-07-11 this register is not applicab le and is not used in iom-2 mode. it is only enabled in pcm/microcontroller mode. 27 h pcmx3 pcm transmit register 3 00 h y bit 76543210 x3- hw x3-ts[6:0] x3-hw selection of the pcm highway for tr ansmitting confer encing data for conference channel b + s or b + d or the lower byte of the first data sample if a linear 16-khz pcm mode is selected. x3-hw = 0 pcm highway a is selected. x3-hw = 1 pcm highway b is selected. x3-ts[6:0] selection of the pcm timeslot used for transmitting data (see description of pcmx1 register).
duslic preliminary data sheet 196 ds3, 2003-07-11 this register is not applicab le and is not used in iom-2 mode. it is only enabled in pcm/microcontroller mode. 28 h pcmx4 pcm transmit register 4 00 h y bit 76543210 x4- hw x4-ts[6:0] x4-hw selection of the pcm highway for tr ansmitting confer encing data for conference channel b + c or the lower byte of the first data sample if a linear 16-khz pcm mode is selected. x4-hw = 0 pcm highway a is selected. x4-hw = 1 pcm highway b is selected. x4-ts[6:0] selection of the pcm timeslot used for transmitting data (see description of pcmx1 register).
duslic preliminary data sheet 197 ds3, 2003-07-11 register setting is only active if bit test-en in register lmcr1 is set to 1. 29 h tstr1 test register 1 00 h ty bit 76543210 pd-ac- pr pd-ac- po pd-ac- ad pd-ac- da pd-ac- gn pd- gnkc pd- ofhc pd- ovtc pd-ac-pr ac-prefi power down pd-ac-pr = 0 normal operation. pd-ac-pr = 1 power down mode. pd-ac-po ac-pofi power down pd-ac-po = 0 normal operation. pd-ac-po = 1 power down mode. pd-ac-ad ac-adc power down pd-ac-ad = 0 normal operation. pd-ac-ad = 1 power down mode, transmit path is inactive. pd-ac-da ac-dac power down pd-ac-da = 0 normal operation. pd-ac-da = 1 power down mode , receive path is inactive. pd-ac-gn ac-gain power down pd-ac-gn = 0 normal operation. pd-ac-gn = 1 power down mode. pd-gnkc ground key comparator (gnk c) is set to power down pd-gnkc = 0 normal operation. pd-gnkc = 1 power down mode.
duslic preliminary data sheet 198 ds3, 2003-07-11 pd-ofhc off-hook comparator (ofhc) power down pd-ofhc = 0 normal operation. pd-ofhc = 1 power down mode. pd-ovtc overtemperature comparator (ovtc) power down pd-ovtc = 0 normal operation. pd-ovtc = 1 power down mode.
duslic preliminary data sheet 199 ds3, 2003-07-11 register setting is only active if bit test-en in register lmcr1 is set to 1. 2a h tstr2 test register 2 00 h ty bit 76543210 pd-dc- pr 0pd-dc- ad pd-dc- da pd- dcbuf 0pd- ttx-a pd-hvi pd-dc-pr dc-prefi power down pd-dc-pr = 0 normal operation. pd-dc-pr = 1 pow er down mode. pd-dc-ad dc-adc power down pd-dc-ad = 0 normal operation. pd-dc-ad = 1 power down mode, transmit path is inactive. pd-dc-da dc-dac power down pd-dc-da = 0 normal operation. pd-dc-da = 1 power down mode , receive path is inactive. pd-dcbuf dc-buffer power down pd-dcbuf = 0 normal operation. pd-dcbuf = 1 power down mode. pd-ttx-a ttx adaptation dac an d pofi power down pd-ttx-a = 0 normal operation. pd-ttx-a = 1 power down mode. pd-hvi hv interface (to slic -e/-e2/-p) power down pd-hvi = 0 normal operation. pd-hvi = 1 power down mode.
duslic preliminary data sheet 200 ds3, 2003-07-11 register setting is only active if bit test-en in register lmcr1 is set to 1. 2b h tstr3 test register 3 00 h ty bit 76543210 00ac- dlb- 4m ac- dlb- 128k ac- dlb- 32k ac- dlb- 8k 00 ac-dlb-4m ac digital loop via a 4- mhz bitstream. (loop encloses all digital hardware in the ac path. together wi th dlb-dc, a pure digital test is possible because there is no infl uence from the analog hardware.) ac-dlb-4m = 0 normal operation. ac-dlb-4m = 1 digital loop closed. ac-dlb-128k ac digital loop via 128 khz ac-dlb-128k = 0 normal operation. ac-dlb-128k = 1 digital loop closed. ac-dlb-32k ac digital loop via 32 khz ac-dlb-32k = 0 normal operation. ac-dlb-32k = 1 digital loop closed. ac-dlb-8k ac digital lo op via 8 khz ac-dlb-8k = 0 normal operation. ac-dlb-8k = 1 digital loop closed.
duslic preliminary data sheet 201 ds3, 2003-07-11 register setting is only active if bit test-en in register lmcr1 is set to 1. 2c h tstr4 test register 4 00 h ty bit 76543210 opim- an opim- 4m cor-64 cox-16 0 0 0 0 opim-an open impedance matching loop in the analog part. opim-an = 0 normal operation. opim-an = 1 loop opened. opim-4m open fast digital impedance matching loop in the ha rdware filters. opim-4m = 0 normal operation. opim-4m = 1 loop opened. cor-64 cut off the ac receive path at 64 khz (just before the im filter). cor-64 = 0 normal operation. cor-64 = 1 receive path is cut off. cox-16 cut off the ac transmit path at 16 khz.(the th filters can be tested without the influence of the analog part.) cox-16 = 0 normal operation. cox-16 = 1 transmit path is cut off.
duslic preliminary data sheet 202 ds3, 2003-07-11 register setting is only active if bit test-en in register lmcr1 is set to 1. 2d h tstr5 test register 5 00 h ty bit 76543210 000dc- pofi- hi dc- hold 000 dc-pofi-hi higher value for dc post filter limit dc-pofi-hi = 0 limit frequency is set to 100 hz (normal operation). dc-pofi-hi = 1 limit frequency is set to 300 hz. dc-hold actual dc output value hol d (value of the last d sp filter stage will be kept) dc-hold = 0 normal operation. dc-hold = 1 dc ou tput value hold.
duslic preliminary data sheet 203 ds3, 2003-07-11 5.2.2 cop command the coefficient operation (cop) command gi ves access to the cram data of the dsps. it is organized in the same way as the sop command. the offset value allows a direct as well as a block access to the cram. writ ing beyond the allowed of fset will be ignored, reading beyond it wi ll give unpredictable results. the value of a specific cram coefficient is calculated by the duslicos software. attention: to ensure proper functionality, it is essenti al that all unused register bits have to be filled with zeros. bit 76543210 byte 1 rd 1 adr[2:0] 1 0 1 byte 2 offset[7:0] rd read data rd = 0 write data to chip. rd = 1 read data from chip. adr[2:0] channel address for the subsequent data adr[2:0] = 0 0 0 channel a adr[2:0] = 0 0 1 channel b (other codes reserv ed for future use)
duslic preliminary data sheet 204 ds3, 2003-07-11 offset [7:0] short name long name 00 h th1 transhybrid filter coefficients part 1 08 h th2 transhybrid filter coefficients part 2 10 h th3 transhybrid filter coefficients part 3 18 h frr frequency-response filter co efficients receive direction 20 h frx frequency-response filter co efficients transmit direction 28 h ar amplification/attenuation stage coefficients receive 30 h ax amplification/attenuation stage coefficients transmit 38 h ptg1 tone generator 1 coefficients 40 h ptg2 tone generator 2 coefficients 48 h lpr low pass filter coefficients receive 50 h lpx low pass filter coefficients transmit 58 h ttx teletax coefficients 60 h im1 impedance matching filt er coefficients part 1 68 h im2 impedance matching filt er coefficients part 2 70 h ringf ringer frequency and amplit ude coefficients (dc loop) 78 h rampf ramp generator coefficients (dc loop) 80 h dcf dc characteristics co efficients (dc loop) 88 h hf hook threshold c oefficients (dc loop) 90 h tpf low-pass filter co efficients (dc loop) 98 h reserved
duslic preliminary data sheet 205 ds3, 2003-07-11 cram coefficients are enabled by setting bit cram-en in re gister bcr3 to 1, except coefficients marked 1) and 2) : coefficients marked 1) are enabled by setting bit ptg in register dscr to 1. coefficients marked 2) are enabled by setting bit lp rx-cr in regist er bcr3 to 1. table 35 cram coefficients byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 offset [7:0] transhybrid coefficient part 1 00 h th1 transhybrid coefficient part 2 08 h th2 transhybrid coefficient part 3 10 h th3 fir filter in receive direction 18 h frr fir filter in transmit direction 20 h frx lm threshold 2nd gain stage receive 1st gain stage receive 28 h ar band-pass for ac lm conference gain lm- ac 2nd gain stage transmit 1st gain stage transmit 30 h ax tg1 band-pass tg1 gain tg1 frequency 38 h ptg1 1) tg2 band-pass tg2 gain tg2 frequency 40 h ptg2 1) lpr 48 h lpr 2) lpx 50 h lpx 2) fir filter for ttx ttx slope ttx level 58 h ttx im k factor im fir filter 60 h im1_f im 4 mhz filter im wdf filter 68 h im2_f lm dc gain ring generator amplitude ring generator frequency ring generator low-pass ring offset ro1 70 h ringf extended battery feeding gain soft reversal end constant ramp cr soft ramp ss ring delay rd 78 h rampf res. in resistive zone r k12 res. in constant current zone r i constant current i k1 knee voltage v k1 open circuit volt. v lim 80 h dcf hook message waiting hook threshold ac ring trip hook threshold ring hook threshold active hook threshold power down 88 h hf ring offset ro3 ring offset ro2 voltage level v tr dc low-pass filter tp2 dc low-pass filter tp1 90 h tpf reserved 98 h 16151413121110987654321
duslic preliminary data sheet 206 ds3, 2003-07-11 5.2.2.1 cram programming ranges table 36 cram programming ranges parameter programming range constant current i k1 0...50 ma, ? <0.5ma hook message waiting, hook thresholds 0..25 ma, ? <0.7ma 25...50 ma, ? <1.3ma ring generator frequency f ring 3..40 hz, ? <1hz 40..80 hz, ? <2hz > 80 hz, ? <4hz ring generator amplitude 0..20 v, ? <1.7v 20..85 v, ? <0.9v ring offset ro1, ro2, ro3 0..25 v, ? <0.6v 25..50 v, ? <1.2v 50..100 v, ? <2.4v, max. 150v knee voltage v k1 , open circuit voltge v lim 0..25 v, ? <0.6v 25..50 v, ? <1.2v >50v, ? <2.4v resistance in resistive zone r k12 0..1000 ? , ? <30 ? resistance in constant current zone r i 1.8 k ? ..4.8 k ? , ? <120 ? 4.8 k ? ..9.6 k ? , ? <240 ? 9.6 k ? ..19 k ? , ? <480 ? 19 k ? ..38 k ? , ? < 960 ? , max. 40 k ?
duslic preliminary data sheet 207 ds3, 2003-07-11 5.2.3 pop command the signal processing oper ation programming (pop) comma nd provides access to the enhanced digital signal processor (edsp) regist ers of the slicofi-2. before using an edsp func tion the according pop regi sters have to be programmed. any change in any of the po p registers (except register s cis-dat and cis/lec-mode) is only updated with enabli ng the corresponding device. for example a change of the center frequency f c of the utd is handled by chang ing the register s utd-cf-h and utd-cf-l, switching off the ut d and switching it on again. the pop registers do no have default values after any kind of reset. attention: to ensure proper f unctionality, the pop registers have to be programmed before edsp-en = 1 . furthermore, all unused pop register bits mu st be filled with zeros. 5.2.3.1 sequence for pop register programming please note that the nlp coefficients shar e the memory location with dtmf and lec coefficients. the coefficients are programmed in the following order (before the first activation of the edsp all pop registers have to be progra mmed. by activation of the individual functions the cont ents of the double-used regist ers are then taken over.): 1. program the lec coefficients. by setting bit lec-en in regi ster bcr5 to 1, the coeffici ents are copied into the edsp and the lec is activated. 2. program the dtmf coefficients. by setting bit dtmf-en in register bcr5 to 1, the coefficient s are copied into the edsp and the dtmf receiver is activated. 3. program the nlp coefficients. by setting bit nlp-en in pop register cis/ lec-mode to 1, the coefficients are copied into the edsp and the nlp is activated. please no te that the nlp can only be activated, when also the lec is active. if the nlp coefficients have been programmed in a prior session, it is possible to activate the nlp using the old nlp config uration by setting bit nlp-oldc in pop register nlp-ctrl to 1. attention: nlp coefficients are only available with slicofi-2 version 1.5
duslic preliminary data sheet 208 ds3, 2003-07-11 5.2.3.2 pop register overview attention: nlp coefficients are only available with slicofi-2 version 1.5 00 h cis-dat caller id sender data buffer (write-only) 30 h dtmf-lev dtmf receiver level byte 0be 30 h nlp-pow-lpf nlp power estima tion lp fast time constant pow-lpf 31 h dtmf-twi dtmf receiver twist byte twi 31 h nlp-pow-lps nlp power estima tion lp slow time constant pow-lps 32 h dtmf-ncf-h dtmf receiver notch filter center frequency high byte ncf-h 32 h nlp-bn-lev-x nlp background noise estimation transmit level bn-lev-x 33 h dtmf-ncf-l dtmf receiver notch filter center frequency low byte ncf-l 33 h nlp-bn-lev-r nlp background noise estimation receive level bn-lev-r 34 h dtmf-nbw-h dtmf receiver notch filter bandwidth high byte nbw-h 34 h nlp-bn-inc nlp background noise estimation increment bn-inc 35 h dtmf-nbw-l dtmf receiver notch filter bandwidth low byte nbw-l 35 h nlp-bn-dec nlp background noise estimation decrement bn-dec
duslic preliminary data sheet 209 ds3, 2003-07-11 36 h dtmf-gain gain stage control for dtmf input signal em 36 h nlp-bn-max nlp background noise estimation maximum noise bn-max 37 h nlp-bn-adj nlp background noise estimation noise adjustment bn-adj 38 h nlp-re-min-erll nlp residual echo minimum erl for lec + line re-min-erll 39 h nlp-re-est-erll nlp residual ec ho estimated erl for lec + line re-est-erll 3a h lec-len line echo cancellation length len 3a h nlp-sd-lev-x nlp speech detection transmit direction level sd-lev-x 3b h lec-powr line echo cancellation power detection level powr 3b h nlp-sd-lev-r nlp speech detection receive direction level sd-lev-r 3c h lec-delp line echo cancellation delta power delp 3c h nlp-sd-lev-bn nlp speech detection bn level sd-lev-bn 3d h lec-delq line echo cancellation delta quality delq 3d h nlp-sd-lev-re nlp speech detection re level sd-lev-re
duslic preliminary data sheet 210 ds3, 2003-07-11 3e h lec-gain-xi line echo cancellation input gain transmit em 3e h nlp-sd-ot-dt nlp speech detection overhang tone for double talk sd-ot-dt 3f h lec-gain-ri line echo cancellation input gain receive em 3f h nlp-erl-lin-lp nlp echo return loss line lp time constant erl-lin-lp 40 h lec-gain-xo line echo cancellation output gain transmit em 40 h nlp-erl-lec-lp nlp echo return loss lec lp time constant erl-lec-lp 41 h nlp-ct-lev-re nlp control re level ct-lev-re 42 h nlp-ctrl nlp control 0 0 0 0 0 nlp-nm nlp-ng nlp-oldc 43 h cis-lev-h caller id sender level high byte lev-h 44 h cis-lev-l caller id sender level low byte lev-l 45 h cis-brs caller id sender buffer request size brs 46 h cis-seiz-h caller id sender number of seizure bits high byte seiz-h
duslic preliminary data sheet 211 ds3, 2003-07-11 47 h cis-seiz-l caller id sender number of seizure bits low byte seiz-l 48 h cis-mark-h caller id sender number of mark bits high byte mark-h 49 h cis-mark-l caller id sender number of mark bits low byte mark-l 4a h cis/lec-mode cis/lec mode setting lec-adapt lec-freeze utdx-sum ut dr-sum 0 nlp-en cis-frm cis-v23 4b h utd-cf-h universal tone detection center frequency high byte cf-h 4c h utd-cf-l universal tone detection center frequency low byte cf-l 4d h utd-bw-h universal tone detection bandwidth high byte bw-h 4e h utd-bw-l universal tone detection bandwidth low byte bw-l 4f h utd-nlev universal tone detection noise level nlev 50 h utd-slev-h universal tone detection signal level high byte slev-h 51 h utd-slev-l universal tone detection signal level low byte slev-l
duslic preliminary data sheet 212 ds3, 2003-07-11 52 h utd-delt universal tone detection delta delt-h 53 h utd-rbrk universal tone detection recognition break time rbrk 54 h utd-rtime universal tone detection recognition time rtime 55 h utd-ebrk utd allowed tone end detection break time ebrk 56 h utd-etime utd tone end detection time etime
duslic preliminary data sheet 213 ds3, 2003-07-11 5.2.3.3 pop register description attention: nlp coefficients are only available with slicofi-2 version 1.5 00 h cis-dat caller id sender data buffer (write-only) y bit 76543210 byte 0 byte 1 byte 2 byte 47
duslic preliminary data sheet 214 ds3, 2003-07-11 minimum dtmf signal de tection level level dtmfdet for dtmf detection in transmit: level dtmfdet [db] = level dtmfdet [dbm0]?3.14+g dtmf [db] level dtmfdet [db] = level dtmfdet [dbm] ? l x [dbr] ? 3.14 + g dtmf [db] for dtmf detection in receive: level dtmfdet [db] = level dtmfdet [dbm0] ? 3.14 + ar1[db] + g dtmf [db] level dtmfdet [db] = level dtmfdet [dbm] ? l r [dbr] ? 3.14 + ar1[db] + g dtmf [db] ar1[db]: the exact value fo r ar1 is shown in the duslicos result file; approximate value ar1 l r for l r ?2 dbr, ar1 ?2 db for l r > ?2 dbr. level dtmfdet [db]=?30?b?3 e[db] ?54 db level dtmfdet ?30 db with 0 e 7 0 b 3 alternative representation b = mod[(?level dtmfdet [db] ? 30),3] e = int[(?level dtmfdet [db] ? 30)/3] note: mod = modulo functi on, int = integer function 30 h dtmf-lev dtmf receiver level byte y bit 76543210 0be
duslic preliminary data sheet 215 ds3, 2003-07-11 nlp power estimation low pa ss fast time constant: the t pow-lpf time constant is used for increasing signals. pow-lpf = 255/t pow-lpf [ms] 1ms t pow-lpf 255 ms 30 h nlp-pow- lpf nlp power estimation lp fast time constant y bit 76543210 pow-lpf table 37 range of t pow-lpf pow-lpf t pow-lpf [ms] 0xff 1 ? 0x01 255
duslic preliminary data sheet 216 ds3, 2003-07-11 dtmf receiver twist byte: the dtmf receiver twist byte defines t he maximum allowed diff erence between the signal levels of the two tones for dtmf detection: twi = 2 twist acc [db] 0db twist acc 12 db 31 h dtmf-twi dtmf receiver twist byte y bit 76543210 twi table 38 range of twist acc pow-lps twist acc [db] 0x00 0 ? 0x18 12
duslic preliminary data sheet 217 ds3, 2003-07-11 nlp power estimation low pa ss slow time constant: the t pow-lps time constant is used for decreasing signals. pow-lps = 1024/t pow-lps [ms] 4ms < t pow-lps 1024 ms this byte belongs to the dtmf-ncf-l byte described on page 219 . 31 h nlp-pow- lps nlp power estimation lp slow time constant y bit 76543210 pow-lps table 39 range of t pow-lps pow-lps t pow-lps [ms] 0xff 4 ? 0x01 1024 32 h dtmf-ncf-h dtmf receiver notch filter center frequency high byte y bit 76543210 ncf-h
duslic preliminary data sheet 218 ds3, 2003-07-11 nlp background noise esti mation transmit level: if the transmit signal s lec,tin ( figure 24 ) is below pow bn-lev-x and the receive signal is below pow bn-lev-r (see page 220 ), the background noise es timator uses the transmit signal for the background no ise estimation. otherwise th e background noise estimator is frozen. pow bn-lev-x [db] = s x,bn-lev [dbm0]?3.14+g lec-xi [db] ? 20*log 10 ( /2) s x,bn-lev [dbm0]: power detection leve l at digital output fo r freezing the background noise estimator bn-lev-x = (6.02 16 + pow bn-lev-x [db]) 2/(5 log 10 2) = (96.32 + pow bn-lev-x [db]) 1.329 ?96 db pow bn-lev-x 0db 32 h nlp-bn- lev-x nlp background noise estimation transmit level y bit 76543210 bn-lev-x table 40 range of pow bn-lev-x bn-lev-x pow bn-lev-x [db] 0x00 ?96 ? 0x7f 0
duslic preliminary data sheet 219 ds3, 2003-07-11 dtmf receiver notch fi lter center frequency: ncf = 32768 = ncf-l + 256 ncf-h 0hz f ncf 2000 hz the bytes are calcul ated as follows: ncf-l = mod (ncf,256) = ncf & 0x00ff ncf-h = int (ncf/256) = ncf >> 8 the echo of the dial tone can activate the double talk detection which means that the dtmf tone will not be detect ed. therefore a notchfilter ca n be programmed to filter out the echo of the dialtone, beca use the frequency of the dial tone is known. the center frequency and the bandw ith of the notch filt er can be programmed. 33 h dtmf-ncf-l dtmf receiver notch filter center frequency low byte y bit 76543210 ncf-l 2 f ncf hz [] 8000 ---------------------- ?? ?? cos
duslic preliminary data sheet 220 ds3, 2003-07-11 nlp background noise es timation receive level: if the transmit signal is below pow bn-lev-x (see page 218 ) and the receive signal s lec,r (see figure 29 ) is below pow bn-lev-r , the background noise estimator uses the transmit signal for the background no ise estimation. otherwise th e background noise estimator is frozen. pow bn-lev-r [db] = s r,bn-lev [dbm0]?3.14+ar1[db]+g lec-ri [db] ? 20*log 10 ( /2) s r,bn-lev [dbm0]: power detection level at digi tal input for free zing the background noise estimator ar1[db]: the exact value fo r ar1 is shown in the duslicos result file; approximate value ar1 l r for l r ?2 dbr, ar1 ?2 db for l r > ?2 dbr. bn-lev-r = (6.02 16 + pow bn-lev-r [db]) 2/(5 log 10 2) = (96.32 + pow bn-lev-r [db]) 1.329 ?96 db pow bn-lev-r 0db 33 h nlp-bn- lev-r nlp background noise estimation receive level y bit 76543210 bn-lev-r table 41 range of pow bn-lev-r bn-lev-r pow bn-lev-r [db] 0x00 ?96 ? 0x7f 0
duslic preliminary data sheet 221 ds3, 2003-07-11 this byte belongs to the dtmf-nbw-l byte described on page 222 . nlp background noise estimation increment: the t bn-inc increment time constant for the ba ckground noise estima tion will be used, when the input signal is hi gher than the actual esti mated background noise value. bn-inc = 0.680330873 t bn-inc [db/sec.] 1.5 db/sec. t bn-inc 375 db/sec. 34 h dtmf-nbw-h dtmf receiver notch filter bandwidth high byte y bit 76543210 nbw-h 34 h nlp-bn-inc nlp background noise estimation increment y bit 76543210 bn-inc table 42 range of t bn-inc bn-inc t bn-inc [db/sec.] 0x01 1.5 ? 0xff 375
duslic preliminary data sheet 222 ds3, 2003-07-11 dtmf receiver notch filter bandwidth: nbw = 65536 = nbw-l + 256 nbw-h with a = 0hz f nbw 2000 hz nbw l =mod(nbw,256) nbw h =int(nbw/256) 35 h dtmf-nbw-l dtmf receiver notch filter bandwidth low byte y bit 76543210 nbw-l a 1a + ------------ - f nbw hz [] 8000 --------------------------- - ? ?? ?? tan
duslic preliminary data sheet 223 ds3, 2003-07-11 nlp background noise estimation decrement: the t bn-dec decrement time constant for the background noise estimation will be used, when the input signal is lower than the actual esti mated background noise value. bn-dec = 0.680330873 t bn-dec [db/sec.] 1.5 db/sec. t bn-dec 375 db/sec. 35 h nlp-bn- dec nlp background noise estimation decrement y bit 76543210 bn-dec table 43 range of t bn-dec bn-dec t bn-dec [db/sec.] 0x01 1.5 ? 0xff 375
duslic preliminary data sheet 224 ds3, 2003-07-11 dtmf input signal gain: g dtmf [db] = 20 log 10 16 + 20 log 10 [g/32768] 24.08 + 20 log 10 [g/32768] ?24.08 db g dtmf 23.95 db with g=2 (9 - e) (32 + m) and 0 m 31, 0 e 7 alternative representation: choose "e" as the next integer value which is higher than or equal to: 36 h dtmf-gain gain stage control fo r dtmf input signal y bit 76543210 em table 44 ranges of g dtmf [db] dependent on ?e? e dtmf input signal gain g dtmf [db] range 0 23.95 db g dtmf 18.06 db 1 17.93 db g dtmf 12.04 db 7?18.20db g dtmf ?24.08 db table 45 example for dtmf-gain calculation g dtmf [db] g dtmf e m dtmf-gain 01300x60 ?6.02 0.5 4 0 0x80 6.02 2 2 0 0x40 36 h nlp-bn- max nlp background noise estimation maximum noise y e 3g 2dtmf 3 g 10 dtmf log 2 10 log -------------------------------- ? 3 g dtmf db [] 6.02 ------------------------------- ? = log ? mg dtmf 2 2e + 32 10 g dtmf db [] 20 ------------------------------ 2 2e + 32 ? = ? =
duslic preliminary data sheet 225 ds3, 2003-07-11 nlp background noise es timation maximum noise: the maximum allowed backgro und noise bn-max is a coef ficient that limits the background noise estimator so that the estimated backg round noise cannot exceed s x,bn-max . pow bn-max [db] = s x,bn-max [dbm0]?3.14?g lec-xo [db] ? 20*log 10 ( /2) s x,bn-max [dbm0]: maximum background noise at digital output bn-max = (6.02 16 + pow bn-max [db]) 2/(5 log 10 2) = (96.32 + pow bn-max [db]) 1.329 ?96 db pow bn-max 0db bit 76543210 bn-max table 46 range of pow bn-max bn-max pow bn-max [db] 0x00 ?96 ? 0x7f 0
duslic preliminary data sheet 226 ds3, 2003-07-11 nlp background noise esti mation noise adjustment: the bn-adj coefficient adjusts the estimated background noise. it is possible to subtract (delta bn-adj < 0) or to add (delta bn-adj > 0) a constant level of noise from (to) the estimated background noise. bn-adj = delta bn-adj [db] 2/(5 log 10 2) = delta bn-adj [db] 1.329 ?96 db delta bn-adj 96 db 37 h nlp-bn- adj nlp background noise estimation noise adjustment y bit 76543210 bn-adj table 47 range for delta bn-adj bn-adj delta bn-adj [db] 0x81 ?96 ? 0x7f 96
duslic preliminary data sheet 227 ds3, 2003-07-11 nlp residual echo minimum ec ho return loss for lec + line: the re-min-erll coefficients defines, wh en the nlp should switch from the simple mode to the comfort mo de. if the estimated echo return lo ss for the hybrid plus the echo return loss for the le c is higher than erll re-min , the nlp switches to the comfort mode. in comfort mode, the nl p estimates the resid ual echo by itself. re-min-erll = (2/(5 log 10 2)) erll re-min [db] erll re-min [db] = s lec,r [db] ? s lec,tout [db] = s r ? s x + ar1 + g lec,ri + g lec,x0 (see figure 29 ) the echo return loss is the difference between th e signal level in receive direction s r and the echo level in tr ansmit direction s x . 0db erll re-min 96 db 38 h nlp-re- min-erll nlp residual echo minimum erl for lec + line y bit 76543210 re-min-erll table 48 range of erll re-min re-min-erll erll re-min [db] 0x00 0 ? 0x7f 96
duslic preliminary data sheet 228 ds3, 2003-07-11 nlp residual echo estimated echo return loss for lec + line: after being enabled, the nlp ha s no information regarding th e echo return loss of the hybrid and the lec. therefor e the nlp has two modes for th e residual echo estimation: a simple mode, which is used after the nlp activation and a comfort mode which is used when the internal filters have usable values. in the simple mode the equation for the residual echo re is: re = s lec,r ?erll re-est due to the equation above, erll re-est should be equal to th e worst case echo return loss for the hybrid (which is exactly the worst case echo return loss between the lec receive input signal and the lec transmit input signal). for duslic, the worst case echo return loss can be estimated by: erll re-est = ar1 + g lec,ri + g lec,xi ? l r + l x ar1[db]: the exact value fo r ar1 is shown in the duslicos result file; approximate value ar1 l r for l r ?2 dbr, ar1 ?2 db for l r > ?2 dbr. for l r ?2 dbr: erll re-est g lec,ri + g lec,xi + l x a negative erll re-est value means that there is gain in the loop while a positive erll re- est value means that there is attenuation in the loop. re-est-erll = erll re-est [db] 2/(5 log 10 2) = erll re-est [db] 1.329 ?96 db erll re-est 96 db 39 h nlp-re- est-erll nlp residual echo estimated erl for lec + line y bit 76543210 re-est-erll table 49 range of erll re-est re-est-erll erll re-est [db] 0x81 ?96 ? 0x7f 96
duslic preliminary data sheet 229 ds3, 2003-07-11 line echo cancellation length: len = lec length[ms]/0.125 lec length has to be entere d in multiples of 0.125 ms. the selected lec length has to be higher than the maximum li ne echo length but not higher than 8 ms. 0.125 ms lec length 8ms 3a h lec-len line echo cancellation length y bit 76543210 len table 5-1 range of lec length len lec length 0x01 0.125 ms ? 0x40 8 ms
duslic preliminary data sheet 230 ds3, 2003-07-11 nlp speech detection tr ansmit direction level: as a condition for valid speech detection in transmit directio n, the transmit signal level has to be hi gher than s sd-lev-x . for other conditions see sd-lev-bn on page 234 and sd-lev-re on page 236 . s sd-lev-x [db] = s x + g lec,xi sd-lev-x = (2/(5 log 10 2)) (96.3 + s sd-lev-x [db]) ?96 db s sd-lev-x 0db 3a h nlp-sd- lev-x nlp speech detection transmit direction level y bit 76543210 sd-lev-x table 50 range of s sd-lev-x sd-lev-x s sd-lev-x [db] 0x00 ?96 ? 0x7f 0
duslic preliminary data sheet 231 ds3, 2003-07-11 minimum power detection level for line echo cancellation: pow lecr [db] = s r,lec-powr [dbm0] ? 3.14 + ar1[db] + g lec-ri [db] ? 20*log 10 ( /2) s r,lec-powr [dbm0]: minimum power detection le vel for line echo cancellation at digital input ar1[db]: the exact value fo r ar1 is shown in the duslicos result file; approximate value ar1 l r for l r ?2 dbr, ar1 ?2 db for l r > ?2 dbr. powr = (6.02 16 + pow lecr [db]) 2/(5 log 10 2) = (96.32 + pow lecr [db]) 1.329 ?96 db pow lecr 0db example: ar1 = ?3 db s r,lec-powr =?40dbm0 pow lecr = ?46.14 db powr = 66.69 67 = 0x43 3b h lec-powr line echo cancellation power detection level y bit 76543210 powr table 51 range of pow lecr powr pow lecr [db] 0x00 ?96 ? 0x7f 0
duslic preliminary data sheet 232 ds3, 2003-07-11 nlp speech detection re ceive direction level: if the receive signal level is below s sd-lev-r , the receive speech de tector doesn't detect speech. the transmit and rece ive speech detectors are used for detecting double talk. sd-lev-r = (2/(5 log 10 2)) (96.3 + s sd-lev-r [db]) s sd-lev-r =s r + ar1 + g lec,ri ?96 db s sd-lev-r 0db 3b h nlp-sd- lev-r nlp speech detection receive direction level y bit 76543210 sd-lev-r table 52 range of s sd-lev-r sd-lev-r s sd-lev-r [db] 0x00 ?96 ? 0x7f 0
duslic preliminary data sheet 233 ds3, 2003-07-11 line echo cancellation delta power for double talk detection (dtd): deltap lec [db] = (s r ?s x ) dtdthr [db] + ar1[db] + g lec-ri [db] ? g lec-xi [db] (s r ?s x ) dtdthr [db]: double talk detection threshold ar1[db]: the exact value fo r ar1 is shown in the duslicos result file; approximate value ar1 l r for l r ?2 dbr, ar1 ?2 db for l r > ?2 dbr. delp = deltap lec [db] 2/(5 log 10 2) = deltap lec [db] 1.329 ?96 db deltap lec 96 db example: ar1 = ?3 db expected echo signal < ?15 db (s r ?s x ) dtdthr =?15db deltap lec =12db delp = 16 = 0x10 3c h lec-delp line echo cancella tion delta power y bit 76543210 delp table 53 range of deltap lec delp deltap lec [db] 0x81 ?96 0x80 no detection ? 0x7f 96
duslic preliminary data sheet 234 ds3, 2003-07-11 nlp speech detection ba ckground noise level: as a condition for valid speech detection in transmit directio n, the transmit signal level s x has to be higher than the esti mated background noise plus delta sd-lev-bn . for other conditions see sd-lev-x on page 230 and sd-lev-re on page 236 . sd-lev-bn = (2/(5 log 10 2)) delta sd-lev-bn [db]) 0db delta sd-lev-bn 96 db 3c h nlp-sd- lev-bn nlp speech detection receive bn level y bit 76543210 sd-lev-bn table 54 range of delta sd-lev-bn sd-lev-bn delta sd-lev-bn [db] 0x00 0 ? 0x7f 96
duslic preliminary data sheet 235 ds3, 2003-07-11 line echo cancellation de lta quality between shadow filter and main filter: the higher deltaq is, the less copying between shadow filter and main filter takes place and the higher is the quality. delq = deltaq[db] 2/(5 log 10 2) = deltaq[db] 1.329 0db deltaq 10 db 3d h lec-delq line echo cancella tion delta quality y bit 76543210 delq table 55 examples for deltaq delq deltaq[db] 0x08 6.02 0x04 3.01 (typical) 0x03 2.26 0x02 1.505
duslic preliminary data sheet 236 ds3, 2003-07-11 nlp speech detection residual echo level: as a condition for valid speech detection in transmit directio n, the transmit signal level s x has to be higher th an the estimated residu al echo plus delta sd-lev-re . therefore, sd-lev-re prevents false decisions of the s peech detector. a false decision can be a too optimistic estimation for the lec echo return loss. du e to the hangover time for double talk (see sd-ot-dt on page 238 ), this level should be higher than the control level residual echo coef ficient (see ct-lev-re on page 243 ). for other valid speec h detection condition s see sd-lev-x on page 230 and sd-lev-bn on page 234 . sd-lev-re = (2/(5 log 10 2)) delta sd-lev-re [db]) 0db delta sd-lev-re 96 db 3d h nlp-sd- lev-re nlp speech detection receive re level y bit 76543210 sd-lev-re table 56 range of delta sd-lev-re sd-lev-re delta sd-lev-re [db] 0x00 0 ? 0x7f 96
duslic preliminary data sheet 237 ds3, 2003-07-11 line echo cancellation input gain transmit: it is important, that g lec-xi [db] will not be changed, so g lec-xi [db] = ?g lec-x0 [db] g lec-xi [db] = 20 log 10 16 + 20 log 10 [g/32768] 24.08 + 20 log 10 [g/32768] ?24.08 db g lec-xi 23.95 db with g=2 9-e (32 + m) and 0 m 31, 0 e 7 alternative representation: choose "e" as the next in teger number which is bi gger than or equal to: 3e h lec-gain-xi line echo cancellation input gain transmit y bit 76543210 em table 57 ranges of g lec-xi [db] dependent on ?e? e input gain g lec-xi [db] range 0 23.95 db g lec-xi 18.06 db 1 17.93 db g lec-xi 12.04 db 7?18.20db g lec-xi ?24.08 db table 58 example for lec-gain-xi calculation g lec-xi [db] g lec-xi e m lec-gain-xi 01300x60 ?6.02 0.5 4 0 0x80 6.02 2 2 0 0x40 e3 g 2lecxi ? 3 g 10 lec xi ? log 2 10 log ------------------------------------- ? 3 g lec xi ? db [] 6.02 ------------------------------------ - ? = log ? mg lec xi ? 2 2e + 32 10 g lec xi ? db [] 20 ----------------------------------- 2 2e + 32 ? = ? =
duslic preliminary data sheet 238 ds3, 2003-07-11 nlp speech detection overha ng time for double talk: double talk exists, when speech is detected at the same time by the receive and the transmit speech detector. in th at case, the nlp will be bypa ssed. to make sure that the silent end of a speech signa l can pass the nlp, the bypass is extended by the overhang time t sd-ot-dt . sd-ot-dt = 0.5 t sd-ot-dt [ms] 2ms t sd-ot-dt 500 ms 3e h nlp-sd- ot-dt nlp speech detectio n overhang time for double talk y bit 76543210 sd-ot-dt table 59 range of t sd-ot-dt sd-ot-dt t sd-ot-dt [ms] 0x01 2 ? 0xfa 500
duslic preliminary data sheet 239 ds3, 2003-07-11 line echo cancellation input gain receive: g lec-ri [db] = 20 log 10 16 + 20 log 10 [g/32768] 24.08 + 20 log 10 [g/32768] ?24.08 db g lec-ri 23.95 db with g=2 9-e (32 + m) and 0 m 31, 0 e 7 alternative representation: choose "e" as the next in teger number which is bi gger than or equal to: 3f h lec-gain-ri line echo cancellation input gain receive y bit 76543210 em table 60 ranges of g lec-ri [db] dependent on ?e? e input gain g lec-ri [db] range 0 23.95 db g lec-ri 18.06 db 1 17.93 db g lec-ri 12.04 db 7?18.20db g lec-ri ?24.08 db table 61 example for lec-gain-ri calculation g lec-ri [db] g lec-ri e m lec-gain-ri 01300x60 ?6.02 0.5 4 0 0x80 6.02 2 2 0 0x40 e 3g 2lecri ? 3 g 10 lec ri ? log 2 10 log ------------------------------------- ? 3 g lec ri ? db [] 6.02 ------------------------------------ - ? = log ? mg lec ri ? 2 2e + 32 10 g lec ri ? db [] 20 ----------------------------------- 2 2e + 32 ? = ? =
duslic preliminary data sheet 240 ds3, 2003-07-11 nlp echo return loss line low pass time constant: t erl-lin-lp is a time constant for the hybrid echo return estimation. erl-lin-lp = 16384/t erl-lin-lp [ms] 64.25 ms t erl-lin-lp 16.384 s 3f h nlp-erl- lin-lp nlp echo return lo ss line lp time constant y bit 76543210 erl-lin-lp table 62 range of t erl-lin-lp erl-lin-lp t erl-lin-lp [ms] 0xff 64.25 ? 0x01 16384
duslic preliminary data sheet 241 ds3, 2003-07-11 line echo cancellation output gain transmit: it is important, that g lec-x0 [db] will not be changed, so g lec-x0 [db] = ?g lec-xi [db] g lec-x0 [db] = 20 log 10 16 + 20 log 10 [g/32768] 24.08 + 20 log 10 [g/32768] ?24.08 db g lec-x0 23.95 db with g=2 9-e (32 + m) and 0 m 31, 0 e 7 alternative representation: choose "e" as the next in teger number which is bi gger than or equal to: 40 h lec-gain-xo line echo cancella tion output gain transmit y bit 76543210 em table 63 ranges of g lec-x0 [db] dependent on ?e? e output gain g lec-x0 [db] range 0 23.95 db g lec-x0 18.06 db 1 17.93 db g lec-x0 12.04 db 7?18.20db g lec-x0 ?24.08 db table 64 example for lec-gain-x0 calculation g lec-x0 [db] g lec-x0 e m lec-gain-x0 01300x60 ?6.02 0.5 4 0 0x80 6.02 2 2 0 0x40 e 3g 2 lec x0 ? 3 g 10 lec x0 ? log 2 10 log -------------------------------------- - ? 3 g lec x0 ? db [] 6.02 ------------------------------------- - ? = log ? m g lec x0 ? 2 2e + 32 10 g lec x0 ? db [] 20 ------------------------------------ 2 2e + 32 ? = ? =
duslic preliminary data sheet 242 ds3, 2003-07-11 nlp echo return loss lec low pass time constant: t erl-lec-lp is a time constant for the lec echo return estimation. erl-lec-lp = 16384/t erl-lec-lp [ms] 64.25 ms t erl-lec-lp 16.384 s 40 h nlp-erl- lec-lp nlp echo return loss lec lp time constant y bit 76543210 erl-lec-lp table 65 range of t erl-lec-lp erl-lec-lp t erl-lec-lp [ms] 0xff 64.25 ? 0x01 16384
duslic preliminary data sheet 243 ds3, 2003-07-11 nlp control level residual echo: if the speech level after the lec is above the estimated residu al echo plus delta ct-lev-re , the nlp is inactive (bypasse d). otherwise the nlp is ac tive, when ther e is no double talk. ct-lev-re = (2/(5 log 10 2)) delta ct-lev-re [db]) 0db delta ct-lev-re 96 db 41 h nlp-ct- lev-re nlp control re level y bit 76543210 ct-lev-re table 66 range of delta ct-lev-re ct-lev-re delta ct-lev-re [db] 0x00 0 ? 0x7f 96
duslic preliminary data sheet 244 ds3, 2003-07-11 42 h nlp-ctrl nlp control y bit 76543210 00000nlp- nm nlp- ng nlp- oldc nlp-nm when the echo path is cut of by the nlp, there are two possible ways to add a comfort noise to the line. this ensure s that the subscriber doesnt assume a dead line. nlp-nm = 0 white noise is selected. nlp-nm = 1 sign noise (spectrum sh aped noise) is selected. nlp-ng nlp-ng = 0 the noise generator is off. nlp-ng = 1 the noise generator is active. nlp-oldc nlp-oldc = 0 after the activation of the nlp the coefficients are copied from the i/o-buffer to the local ram. nlp-oldc = 1 the nlp uses the old coefficients.
duslic preliminary data sheet 245 ds3, 2003-07-11 caller id sender level: lev cis [db] = lev cis [dbm0]?3.14?3.37 lev cis [db] = lev cis [dbm] ? l r [dbr] ? 3.14 ? 3.37 lev = 32767 10 (lev cis [db]/20) ?90.31 db lev cis 0db lev-l = mod (lev,256) lev-h = int (lev/256) 43 h cis-lev-h caller id sender level high byte y bit 76543210 lev-h 44 h cis-lev-l caller id sender level low byte y bit 76543210 lev-l table 67 range of lev cis lev lev cis [db] 0 (signal off) 1 ?90.31 32767 0 ?
duslic preliminary data sheet 246 ds3, 2003-07-11 caller id sender buffer request size: 0 brs 46 cis-brs is a threshold to be set within the caller id sende r buffer (cis-dat, 48 bytes). if the number of bytes in t he cid sender buffer falls belo w the buffer request size, an interrupt is generated. this is the indication to fi ll up the buffer again. the first bit will be sent if the number of by tes in the cid sender buffer exceeds the buffer request size (start sending wi th brs + 1 number of bytes). the buffer request size brs must always be smaller than the number of bytes to be sent: brs < number of bytes to be sent typical values: 10 - 30. 45 h cis-brs caller id sender bu ffer request size y bit 76543210 brs
duslic preliminary data sheet 247 ds3, 2003-07-11 caller id sender number of seizure bits: (only if high level framin g is selected in the cis/ lec-mode register (see page 248 )) 0 seiz 32767 seiz-l = mod (seiz,256) seiz-h = int (seiz/256) 46 h cis-seiz-h caller id sender numb er of seizure bits high byte y bit 76543210 seiz-h 47 h cis-seiz-l caller id sender numb er of seizure bits low byte y bit 76543210 seiz-l
duslic preliminary data sheet 248 ds3, 2003-07-11 caller id sender numb er of mark bits: (only if high level fram ing is selected in the cis/lec-mode register) 0 mark 32767 mark-l = mod (mark,256) mark-h = int (mark/256) attention: bit 3 must be set to 0. 48 h cis-mark-h caller id sender number of mark bits high byte y bit 76543210 mark-h 49 h cis-mark-l caller id sender number of mark bits low byte y bit 76543210 mark-l 4a h cis/lec- mode cis/lec mode setting y bit 7 6543210 lec- adapt lec- freeze utdx- sum utdr- sum 0nlp-encis- frm cis- v23
duslic preliminary data sheet 249 ds3, 2003-07-11 lec-adapt line echo cancellation adaptation start. the lec-adapt bit is only evaluated if the lec-en is changed from 0 to 1. to initialize the lec coefficients to 0 requires the lec-adapt bit set to 0 followed by the lec-en bit changed from 0 to 1. it is not possible to reset the lec coefficients to 0 while the lec is running. the lec has to be disabled first by setti ng bit lec-en to 0 and then it is necessary to enable th e lec again (lec-en = 1, lec-adapt = 0). if valid coefficients from a fo rmer lec adaptation are present in the ram, it is possible to activate the lec with this coefficents by setting bit lec-adapt to 1. it is also possible to read out adapted coeffici ents from the lec for external storage and to reuse these co efficients as a start up value for the next connection (see the available application notes). lec-adapt = 0 line echo ca ncellation coefficien ts initialized with zero. lec-adapt = 1 line echo ca ncellation coefficien ts initialized with old coefficients. lec-freeze line echo cancellation adaptation freeze lec-freeze = 0 no freezing of coefficients lec-freeze = 1 freezing of coefficients cis-frm caller id sender framing cis-frm = 0 low-level framing: all data for cid transmissions must be written to the cid buff er including ch annel seizure and mark sequence, st art and stop bits. cis-frm = 1 high-level framing: ch annel seizure and mark sequence as well as start and stop bi ts are automatically inserted by the slicofi-2x. only tr ansmission bytes from the data packet (see figure 30 ) have to be written to the cis buffer. cis-v23 caller id sender mode cis-v23 = 0 bell 202 selected cis-v23 = 1 v.23 selected
duslic preliminary data sheet 250 ds3, 2003-07-11 universal tone detect ion center frequency: cf = 32768 0< f c <4000hz cf-l = mod (cf,256) cf-h = int (cf/256) 4b h utd-cf-h universal tone detection center frequency high byte y bit 76543210 cf-h 4c h utd-cf-l universal tone detection center frequency low byte y bit 76543210 cf-l 2 f c hz [] 8000 ----------------------- - ?? ?? cos
duslic preliminary data sheet 251 ds3, 2003-07-11 universal tone de tection bandwidth: bw = 65536 with a= 0< f bw <2000hz bw-l = mod (bw,256) bw-h = int (bw/256) 4d h utd-bw-h universal tone dete ction bandwidth high byte y bit 76543210 bw-h 4e h utd-bw-l universal tone dete ction bandwidth low byte y bit 76543210 bw-l a 1a + ------------ - f bw hz [] 8000 -------------------------------- - ?? ?? t an
duslic preliminary data sheet 252 ds3, 2003-07-11 universal tone detection noise level: nlev = 32768 10 (lev n [db])/20 ?96 db lev n ?42.18 db 4f h utd-nlev universal tone detection noise level y bit 76543210 nlev
duslic preliminary data sheet 253 ds3, 2003-07-11 universal tone dete ction signal level: calculation for transmit: lev s [db] = lev s [dbm0]?3.14 ?20*log 10 ( /2) lev s [db] = lev s [dbm] ? l x [dbr] ? 3.14 ? 20*log 10 ( /2) calculation for receive: lev s [db] = lev s [dbm0] ? 3.14 + ar1[db] ? 20*log 10 ( /2) lev s [db] = lev s [dbm] ? l r [dbr] ? 3.14 + ar1[db] ? 20*log 10 ( /2) ar1[db]: the exact value fo r ar1 is shown in the duslicos result file; approximate value ar1 l r for l r ?2 dbr, ar1 ?2 db for l r > ?2 dbr. slev = 32768 10 (lev s [db])/20 ?nlev ?96 db lev s 0db signal level: slev-l = mod (slev,256) slev-h = int (slev/256) utd for receive and transmit: by enabling the utd, the coe fficients in the utd regist ers are copied to the main memory. therefore, different coefficients c an be set for receive and transmit direction. 50 h utd-slev-h universal tone dete ction signal level high byte y bit 76543210 slev-h 51 h utd-slev-l universal tone detection signal level low byte y bit 76543210 slev-l
duslic preliminary data sheet 254 ds3, 2003-07-11 universal tone detecti on delta inband/outband: delt = sign(delta utd ) 128 10 ?|delta utd [db]|/20 ?42 db delta utd 42 db example: detection of a tone that is between 1975 hz and 2025 hz f c =2000hz f bw =50hz tone at 2025 hz: outband = ? 3 db, inband = ?3 db (see table 68 ) delta utd =0db delt=128=0x80 f bw =500hz tone at 2025 hz: outband = ?20 db, inband = ?0.04 db (see table 68 ) delta utd 20 db delt = 13 = 0x0d 52 h utd-delt universal tone detection delta y bit 76543210 delt table 68 utd inband /outband attenuation f outband inband f c f bw /0.2 ?0.04 db ?20 db f c f bw /2 ?3 db ?3 db f c f bw /20 ?20 db ?0.04 db f c f bw /200 ?40 db ?0 db
duslic preliminary data sheet 255 ds3, 2003-07-11 allowed recognition break time for universal tone detection: rbrk = rbrktime[ms]/4 rbrktime must be entered in multiples of 4 ms. 0ms rbrktime 1000 ms for an example, see figure 64 . 53 h utd-rbrk universal tone detection recognition break time y bit 76543210 rbrk
duslic preliminary data sheet 256 ds3, 2003-07-11 universal tone detect ion recognition time: rtime = rtime[ms]/16 rtime must be entered in multiples of 16 ms. 0ms rtime 4000 ms figure 64 example for utd recognition timing 54 h utd-rtime universal tone detection recognition time y bit 76543210 rtime duslic_0013_rbrk_timing tone utdi-ok bit (intreg3) utdi-ok bit (intreg3) t t t 1 0 1 0 1 0 rbrktime rbrktime rtime rtime
duslic preliminary data sheet 257 ds3, 2003-07-11 allowed tone end detect ion break time for un iversal tone detection: ebrk = ebrktime [ms] 0ms ebrktime 255 ms for an example, see figure 65 . 55 h utd-ebrk utd allowed tone end detection break time y bit 76543210 ebrk
duslic preliminary data sheet 258 ds3, 2003-07-11 tone end detection time for universal tone detection: etime = etime[ms]/4 etime must be entered in multiples of 4 ms. 0ms etime 1000 ms figure 65 example for utd to ne end detection timing 5.2.3.4 recommended nlp coefficients table 69 shows recommended nlp register va lues and the respective parameter values. 56 h utd-etime utd tone end detection time y bit 76543210 etime tone utdi-ok bit (intreg3) utdi-ok bit (intreg3) t t t 1 0 1 0 1 0 ebrktime ebrktime etime etime duslic_0014_ebrk_timing
duslic preliminary data sheet 259 ds3, 2003-07-11 table 69 recommended nlp coefficients register name register value parameter value nlp-pow-lpf 0x6a t pow-lpf =2.4msec nlp-pow-lps 0x2a t pow-lps = 24.4 msec nlp-bn-lev-x 0x44 pow bn-lev-x =?45.1db nlp-bn-lev-r 0x44 pow bn-lev-r = ?45.1 db nlp-bn-inc 0x10 t bn-inc = 23.5 db/sec nlp-bn-dec 0x40 t bn-dec = 94.1 db/sec nlp-bn-max 0x40 pow bn-max = ?48.0 db nlp-bn-adj 0x04 delta bn-adj =3.0db nlp-re-min-erll 0x10 erll re-min =12.0db nlp-re-est-erll 0x0c erll re-est =9.0db nlp-sd-lev-x 0x44 s sd-lev-x = ?45.1 db nlp-sd-lev-r 0x44 s sd-lev-r = ?45.1 db nlp-sd-lev-bn 0x0c delta sd-lev-bn =9.0db nlp-sd-lev-re 0x10 delta sd-lev-re =12.0db nlp-sd-ot-dt 0x3c t sd-ot-dt = 120.0 msec nlp-erl-lin-lp 0x20 t erl-lin-lp = 512.0 msec nlp-erl-lec-lp 0x10 t erl-lec-lp = 1024.0 msec nlp-ct-lev-re 0x0c delta ct-lev-re =9.0db
duslic preliminary data sheet 260 ds3, 2003-07-11 5.2.4 iom-2 interface command/indication byte the command/indication (c/i) channel is used to comm unicate real time status information and for fast co ntrolling of the duslic. da ta on the c/i channel are continuously transmitted in each frame until new data are sent. data downstream c/i ? channe l byte (receive) ? iom-cidd the first six cidd data bits control the general operati ng modes for both duslic channels. according to the iom-2 specifications , new data must be present for at least two frames to be accepted. ) table 70 m2, m1, m0: ge neral operating mode cidd slicofi-2 operating mode (for details see ?overview of all duslic operating modes? on page 74 ) m2 m1 m0 1 1 1 sleep, power down (pdrx) 0 0 0 power down high impedance (pdh) 0 10any active mode 1 0 1 ringing (actr burst on) 1 1 0 active with metering 1 00ground start 0 01ring pause cidd data downstream c/i ? channel byte n bit 76543210 m2a m1a m0a m2b m1b m0b mr mx m2a, m1a, m0a select operating mode for duslic channel a m2b, m1b, m0b select operating mode for duslic channel b mr, mx handshake bits monito r receive and transmit (see ?iom-2 interface monitor tr ansfer protocol? on page 133 )
duslic preliminary data sheet 261 ds3, 2003-07-11 data upstream c/i ? channe l byte (transmit) ? iom-cidu this byte is used to quickl y transfer the most important an d time-critical information from the duslic. each transfer fr om the duslic lasts for at least 2 consecutive frames. cidu data upstream c/ i ? channel byte 00 h n bit 7 6 5 4 3 2 1 0 int-cha hooka gndka int -chb hookb gndkb mr mx int-cha interrupt information channel a int-cha = 0 no interru pt in channel a int-cha = 1 interrupt in channel a hooka hook informati on channel a hooka = 0 on-hook channel a hooka = 1 off-hook channel a gndka ground key inform ation channel a gndka = 0 no longitudin al current detected gndka = 1 longitudi nal current detect ed in channel a int-chb interrupt information channel b int-chb = 0 no interru pt in channel b int-chb = 1 interrupt in channel b hookb hook informati on channel b hookb = 0 on-hook channel b hookb = 1 off-hook channel b gndkb ground key inform ation channel b gndkb = 0 no longitudin al current detected gndkb = 1 longitudi nal current detect ed in channel b mr, mx handshake bits monitor receive and transmit (see ?iom-2 interface monitor tr ansfer protocol? on page 133 )
duslic preliminary data sheet 262 ds3, 2003-07-11 5.2.5 programming examples of the slicofi-2 5.2.5.1 microcontroller interface sop write to channel 0 starting after th e channel specific read-only registers figure 66 waveform of programming example sop-write to channel 0 sop read from channel 1 readi ng out the interrupt registers the slicofi-2 will send data when it has completely received the second command byte. 01000100 first command byte (sop write for channel 0) 00010101 second comma nd byte (offset to bcr1 register) 00000000 contents of bcr1 register 00000000 contents of bcr2 register 00010001 contents of bcr3 register 00000000 contents of bcr4 register 00000000 contents of bcr5 register 11001100 first command byte (sop read for channel 1). 00000111 second command by te (offset to inte rrupt register 1). 11111111 dump byte (thi s byte is always ff h ). 11000000 interrupt r egister intreg1 (an interrupt has occurred, off-hook was detected). 00000010 interrupt register intreg2 (i/o pin 2 is ?1?). 00000000 interrupt register intreg3 00000000 interrupt register intreg4 command offset bcr1 din dclk cs bcr2 bcr3 bcr4 bcr5 ezm220121
duslic preliminary data sheet 263 ds3, 2003-07-11 figure 67 waveform of programming e xample sop read from channel 0 5.2.5.2 iom-2 interface an example with the same pr ogramming sequence as before, using the iom-2 interface is presented here to show th e differences between the micr ocontroller interface and the iom-2 interface. sop write to channel 0 starting after th e channel-specific read-only registers monitor mr/mx moni tor mr/mx comment data down data up 10000001 10 11111111 01 iom-2 address second byte 01000100 11 11111111 01 first command byte (sop write for channel 0) 01000100 10 11111111 11 first command byte second time 00010101 11 11111111 01 second command by te (offset to bcr1 register) 00010101 10 11111111 11 second command byte second time 00000000 11 11111111 01 contents of bcr1 register 00000000 10 11111111 11 contents of bcr1 register second time 00000000 11 11111111 01 contents of bcr2 register 00000000 10 11111111 11 contents of bcr2 register second time 00010001 11 11111111 01 contents of bcr3 register 00010001 10 11111111 11 contents of bcr3 register second time 00000000 11 11111111 01 contents of bcr4 register 00000000 10 11111111 11 contents of bcr4 register second time 11111111 11 11111111 01 no more information (dummy byte) 11111111 11 11111111 11 s ignaling eom (end of message) by holdin g mx bit at ?1?. because the slicofi-2 has an open command structure, there is no fixed command length. the iom-2 h andshake protocol allows for an in finite length of a data stream. therefore, the host must te rminate the data transfer by sending an end-of-message signal (eom) to the slic ofi-2. the slicofi-2 will abort t he transfer only if the host tries to write or read beyond the allowed maxi mum offset given by the different types of commands. each transfer must start with the slicofi-2- specific iom-2 address (81 h ) ezm220122 dclk cs command offset dump intreg 1 dout din intreg 2 intreg 3 intreg 4
duslic preliminary data sheet 264 ds3, 2003-07-11 and must end with an eom of the handshake bits. app ending a command immediately to its predecessor without an eo m in between is not allowed. when reading interrupt register s, slicofi-2 stops the transf er after the fourth register in iom-2 mode. this is to prevent some host chips from reading 16 bytes because they cannot terminate the tr ansfer after n bytes.
duslic preliminary data sheet 265 ds3, 2003-07-11 sop-read from channel 1 readi ng out the interrupt registers monitor mr/mx monitor mr/mx comment data down data up 10000001 10 1111111111iom -2 address first byte 10000001 10 1111111101iom-2 address second byte 11001100 11 1111111101first command byte (sop read for channel 1) 11001100 10 1111111111first command byte second time 00001000 11 1111111101secon d command byte (offset to interrupt register 1) 00001000 10 1111111111second command byte second time 11111111 11 1111111101acknowledgem ent for the seco nd command byte 11111111 11 1000000110iom-2 address first byte (answer) 11111111 01 1000000110iom-2 address second byte 11111111 01 1100000011inte rrupt register intreg1 11111111 11 1100000010interrupt register intreg1 second time 11111111 01 0000001011inte rrupt register intreg2 11111111 11 0000001010interrupt register intreg2 second time 11111111 01 0000000011inte rrupt register intreg3 11111111 11 0000000010interrupt register intreg3 second time 11111111 01 0000000011inte rrupt register intreg4 11111111 11 0000000010interrupt register intreg4 second time 11111111 11 0100110111slicofi-2 sends the next register 11111111 11 1111111111slico fi-2 aborts transmission
duslic preliminary data sheet 266 ds3, 2003-07-11 5.3 slicofi-2s command structure and programming this section describes only the slic ofi-2s peb 3264 co mmand structure and programming. therefore, this section pertai ns only to the dusl ic-s and duslic-s2 chip sets. 5.3.1 sop command the status operation (sop) command provides access to the configuration and status registers of the slicofi- 2s. common registers chang e the mode of the entire slicofi-2s chip. all ot her registers are channel-specific. it is possible to access single or multiple registers. multiple register access is achieved by an automatic offset increment. write access to read-only regi sters is ignored and does not abort the command sequence. offsets ma y change in future vers ions of the slicofi-2s. attention: to ensure proper functionality, it is essenti al that all unused register bits have to be filled with zeros. 5.3.1.1 sop register overview 00 h revision revision number (read-only) rev[7:0] 01 h chipid 1 chip identification 1 (read-only) for internal use only 02 h chipid 2 chip identification 2 (read-only) for internal use only 03 h chipid 3 chip identification 3 (read-only) for internal use only 04 h fuse1 fuse register 1 for internal use only 05 h pcmc1 pcm configuration register 1 dbl-clk x-slope r-slope no-drive-0 shift pcmo[2:0]
duslic preliminary data sheet 267 ds3, 2003-07-11 06 h xcr extended configuration register 0 asynch-r 0 0 0 0 0 0 07 h intreg1 interrupt register 1 (read-only) int-ch hook gndk gnkp icon vtrlim otemp sync-fail 08 h intreg2 interrupt register 2 (read-only) 0 ready rstat 0 io[4:1]-du 09 h intreg3 interrupt register 3 (read-only) 00000000 0a h intreg4 interrupt register 4 (read-only) 00000000 0b h chkr1 checksum register 1 (high byte) (read-only) sum-ok chksum-h[6:0] 0c h chkr2 checksum register 2 (low byte) (read-only) chksum-l[7:0] 0d h lmres1 level metering result 1 (high byte) (read-only) lm-val-h[7:0] 0e h lmres2 level metering result 2 (low byte) (read-only) lm-val-l[7:0] 0f h fuse2 fuse register 2 for internal use only 10 h fuse3 fuse register 3 for internal use only
duslic preliminary data sheet 268 ds3, 2003-07-11 11 h mask mask register ready-m hook-m gndk-m gnkp-m ic on-m vtrlim-m otemp-m sync-m 12 h ioctl1 i/o control register 1 io[4:1]-inen io[4:1]-m 13 h ioctl2 i/o control register 2 io[4:1]-oen io[4:1]-dd 14 h ioctl3 i/o control register 3 dup[3:0] dup-io[3:0] 15 h bcr1 basic configuration register 1 hir hit 0 revpol actr actl sel-slic[1:0] 16 h bcr2 basic configuration register 2 rext-en soft-dis ttx-dis 1) ttx-12k 2) him-an ac-xgain 0 pdot-dis 17 h bcr3 basic configuration register 3 mu-law lin 0 pcmx-en 0 0 0 cram-en 18 h bcr4 basic configuration register 4 th-dis im-dis ax-dis ar-dis frx-dis frr-dis hpx-dis hpr-dis 19 h reserved 00000000 1a h dscr dtmf sender configuration register dg-key[3:0] cor8 ptg tg2-en tg1-en 1b h reserved 00000000
duslic preliminary data sheet 269 ds3, 2003-07-11 1c h lmcr1 level metering configuration register 1 test-en lm-en lm-thm pcm2dc lm2 pcm lm-once lm-mask dc-ad16 1d h lmcr2 level metering configuration register 2 lm-notch lm-filt lm-rect ramp-en lm-sel[3:0] 1e h lmcr3 level metering configuration register 3 ac-short- en rtr-sel lm-itime[3:0] rng-offset[1:0] 1f h ofr1 offset register 1 (high byte) offset-h[7:0] 20 h ofr2 offset register 2 (low byte) offset-l[7:0] 21 h pcmr1 pcm receive register 1 r1-hw r1-ts[6:0] 22 h reserved 23 h reserved 24 h reserved 25 h pcmx1 pcm transmit register 1 x1-hw x1-ts[6:0]
duslic preliminary data sheet 270 ds3, 2003-07-11 1) only for duslic-s; is set to 1 for duslic-s2. 2) only for duslic-s; is set to 0 for duslic-s2. 26 h reserved 27 h reserved 28 h reserved 29 h tstr1 test register 1 pd-ac-pr pd-ac-po pd-ac-ad pd-ac-da pd-ac-gn pd-gnkc pd-ofhc pd-ovtc 2a h tstr2 test register 2 pd-dc-pr 0 pd-dc-ad pd-dc- da pd-dcbuf 0 pd-ttx-a 2) pd-hvi 2b h tstr3 test register 3 0 0 ac-dlb-4m ac-dlb- 128k ac-dlb- 32k ac-dlb- 8k 00 2c h tstr4 test register 4 opim-an opim-4m cor-64 cox-16 0 0 0 0 2d h tstr5 test register 5 0 0 0 dc-pofi- hi dc-hold 0 0 0
duslic preliminary data sheet 271 ds3, 2003-07-11 5.3.1.2 sop register description 00 h revision revision number (read-only) curr. rev. n bit 76543210 rev[7:0] rev[7:0] current revision number of the slicofi-2s. 01 h chipid 1 chip identificati on 1 (read-only) hw n bit 76543210 for internal use only 02 h chipid 2 chip identificati on 2 (read-only) hw n bit 76543210 for internal use only 03 h chipid 3 chip identificati on 3 (read-only) hw n bit 76543210 for internal use only 04 h fuse1 fuse register 1 hw n bit 76543210 for internal use only
duslic preliminary data sheet 272 ds3, 2003-07-11 05 h pcmc1 pcm configuration register 1 00 h n bit 7 6 5 4 3 210 dbl-clk x-slope r-slope no-drive-0 shift pcmo[2:0] dbl-clk clock mode for the pcm interface (see figure 53 on page 125 ). dbl-clk = 0 single clocking is used. dbl-clk = 1 double clocking is used. x-slope transmit slope (see figure 53 on page 125 ). x-slope = 0 transmission starts wi th rising edge of the clock. x-slope = 1 transmission starts wi th falling edge of the clock. r-slope receive slope (see figure 53 on page 125 ). r-slope = 0 data is sampled with falling edge of the clock. r-slope =1 data is sampled with ri sing edge of the clock. no- drive-0 driving mode for bit 0 (only avai lable in single- clocking mode). no-drive = 0 bit 0 is driven the entire clock period. no-drive = 1 bit 0 is driven during the first half of the clock period only. shift shifts the access edge s by one clock cycle in double clocking mode. shift = 0 no shift takes place. shift = 1 shift takes place. pcmo[2:0] all pcm timing is moved by pcmo da ta periods against the fsc signal. pcmo[2:0] = 0 0 0 no offset is added. pcmo[2:0] =0 0 1 one data period is added. pcmo[2:0] = 1 1 1 seven data periods are added.
duslic preliminary data sheet 273 ds3, 2003-07-11 06 h xcr extended configuration register 00 h n bit 7 6 5 4 3 2 1 0 0asynch -r 000000 asynch-r enables asynchronous ringi ng in case of intern al or external ringing. asynch-r = 0 internal or external ringing with zero crossing selected asynch-r = 1 asynchronous ringing selected.
duslic preliminary data sheet 274 ds3, 2003-07-11 07 h intreg1 interrupt register 1 (read-only) 80 h y bit 76543210 int-ch hook gndk gnkp icon vtrlim otemp sync- fail int-ch interrupt channel bit. th is bit indicates that the correspond ing channel caused the last interrupt. will be set automatically to zero after all interrupt registers have been read. int-ch = 0 no interrupt in corresponding channel. int-ch = 1 interrupt caused by corresponding channel. hook on/off-hook information for the loop in all operating modes, filtered by dup (data upstream persistence) counte r and interrupt generation masked by the hook-m bit. a change of this bit generates an interrupt. hook = 0 on-hook. hook = 1 off-hook. gndk ground key or ground start information via the il pin in all active modes, filtered for ac suppressi on by the dup counter an d interrupt generation masked by the gndk-m bit. a change of this bit generates an interrupt. gndk = 0 no longitudin al current detected. gndk = 1 longitudinal current de tected (ground key or ground start). gnkp ground key polarity. indicate s the active ground key level (positive/negative) inte rrupt generation masked by the gnkp-m bit. a change of this bit generates an interrupt. this bit can be used to obtain information about interf erence voltage influence. gnkp = 0 negative ground ke y threshold level active. gnkp = 1 positive ground ke y threshold level active.
duslic preliminary data sheet 275 ds3, 2003-07-11 icon constant current informati on. filtered by dup-io counter and interrupt generation masked by the icon-m bit. a change of this bit generates an interrupt. icon = 0 resistive or c onstant volt age feeding. icon = 1 constant current feeding. vtrlim exceeding of a programmed voltage threshold for the tip/ring voltage, filtered by the dup-io counter and interrupt generation masked by the vtrlim-m bit. a change of th is bit causes an interrupt. the voltage threshold for the tip/ring voltage is set in cram (calculated with duslicos dc control para meter 2/4: tip-ring threshold). vtrlim = 0 voltage at tip/ ring is below the limit. vtrlim = 1 voltage at tip/ ring is above the limit. otemp thermal overload warning from the sl ic-s/-s2 line drivers masked by the otemp-m bit. an interrupt is only generated if the otemp bit changes from 0 to1. otemp = 0 temperature at slic -s/-s2 is below the limit. otemp = 1 temperature at slic-s/-s2 is above the limit. in case of bit pdot-dis = 0 (register bcr2) the duslic is switched automati cally into pdh mode and otemp is hold at 1 until th e slicofi-2s is set to pdh by a ciop/cidd command. sync-fail failure of the synchronizati on of the iom-2/pcm inte rface. an interrupt is only generated if the sync-fa il bit changes from 0 to 1. resynchronization of the pcm interface can be done with the resynchronization command (see chapter 5 ) sync-fail = 0 synchronization ok. sync-fail = 1 synchro nization failure.
duslic preliminary data sheet 276 ds3, 2003-07-11 after a hardware reset, the rstat bit is set and generates an inte rrupt. therefore, the default value of intreg2 is 20 h . after reading all four inte rrupt registers, the intreg2 value changes to 4f h . 08 h intreg2 interrupt register 2 (read-only) 20 h y bit 76543210 0 ready rstat 0 io[4:1]-du ready indicates whether ramp generator has finished. an in terrupt is only generated if the ready bit changes fr om 0 to 1. at a new start of the ramp generator, the bit is set to 0. for further information regarding soft reversal see chapter 2.7.2.1 . ready = 0 ramp generator active. ready = 1 ramp generator not active. rstat reset status since last interrupt. rstat = 0 no reset has occurr ed since the last interrupt. rstat = 1 reset has occurred since the last interrupt. io[4:1]-du data on i/o pins 1 to 4 filtered by the dup-io counter and interrupt generation masked by the io[4:1]-du -m bits. a change of any of these bits generates an interrupt. 09 h intreg3 interrupt register 3 (read-only) 00 h y bit 76543210 00000000 0a h intreg4 interrupt register 4 (read-only) 00 h y bit 76543210 00000000
duslic preliminary data sheet 277 ds3, 2003-07-11 0b h chkr1 checksum register 1 (high byte) (read-only) 00 h y bit 76543210 sum- ok chksum-h[6:0] sum-ok information about the va lidity of the checksu m. the checksum is valid if the intern al checksum calculat ion is finished. checksum calculation: for (cram_adr = 0 to 159) do cram_dat = cram[cram_adr] csum[14:0] = (csum[13:0] & 1) ?0?) xor (?0000000? & cram_dat[7:0]) xor (?0000000000000? & csu m[14] & csum[14]) end 1) ?&? means a concatenation ; not the logic operation sum-ok = 0 cram che cksum is not valid. sum-ok = 1 cram checksum is valid. chksum-h[6:0] cram checksum high byte
duslic preliminary data sheet 278 ds3, 2003-07-11 0c h chkr2 checksum register 2 (low byte) (read-only) 00 h y bit 76543210 chksum-l[7:0] chksum-l[7:0] cram-checksum low byte 0d h lmres1 level metering result 1 (high byte) (read-only) 00 h y bit76543210 lm-val-h[7:0] lm-val-h[7:0] lm result high byte (selected by the lm-sel bi ts in the lmcr2 register) 0e h lmres2 level metering resu lt 2 (low byte) (read-only) 00 h y bit 76543210 lm-val-l[7:0] lm-val-l[7:0] lm result low byte (selected by the lm-sel bi ts in the lmcr2 register) 0f h fuse2 fuse register 2 hw y bit 76543210 for internal use only 10 h fuse3 fuse register 3 hw y
duslic preliminary data sheet 279 ds3, 2003-07-11 bit 76543210 for internal use only
duslic preliminary data sheet 280 ds3, 2003-07-11 the mask bits in the mask register influence only the generation of an interrupt. even if the mask bit is set to 1, the corresponding status bit in th e intregx regist ers is updated to show the current status of the corresponding event. 11 h mask mask register ff h y bit 76543210 ready -m hook -m gndk -m gnkp -m icon -m vtrlim -m otemp -m sync -m ready-m mask bit for ramp generator ready bit ready-m = 0 an interrupt is generated if the ready bit changes from 0 to 1. ready-m = 1 changes of the ready bit don?t generate interrupts. hook-m mask bit for off-hook detection hook bit hook-m = 0 each change of the ho ok bit generate s an interrupt. hook-m = 1 changes of the hook bit don?t genera te interrupts. gndk-m mask bit for ground ke y detection gndk bit gndk-m = 0 each change of the gn dk bit generate s an interrupt. gndk-m = 1 changes of the gndk bi t do not generate interrupts. gnkp-m mask bit for ground key level gnkp bit gnkp-m = 0 each change of the gnkp bit generates an interrupt. gnkp-m = 1 changes of the gnkp bit do not generate interrupts. icon-m mask bit for constant curr ent information icon bit icon-m = 0 each change of the ic on bit generates an interrupt. icon-m = 1 changes of the icon bi t do not generate interrupts. vtrlim-m mask bit for programmed vo ltage limit vtrlim bit vtrlim-m = 0 each change of the vtrlim bit g enerates an interrupt. vtrlim-m = 1 changes of the vtrlim bit do not generate interrupts.
duslic preliminary data sheet 281 ds3, 2003-07-11 otemp-m mask bit for thermal overload warning otemp bit otemp-m = 0 a change of the otem p bit from 0 to 1 generates an interrupt. otemp-m = 1 a change of the ot emp bit from 0 to 1 does not generate interrupts. sync-m mask bit for synchronization failure sync-fail bit sync-m = 0 a change of the sync-fail bit from 0 to 1 generates an interrupt. sync-m = 1 a change of the sync-fail bit fr om 0 to 1 does not generate interrupts.
duslic preliminary data sheet 282 ds3, 2003-07-11 the mask bits io[4:1]-m influen ce only the generation of an interrupt. even if the mask bit is set to 1, the correspo nding status bit in the intreg x registers is updated to show the current status of the corresponding event. 12 h ioctl1 i/o control register 1 0f h y bit 76543210 io[4:1]-inen io[4:1]-m io4-inen input enable for prog rammable i/o pin io4 io4-inen = 0 input schmitt trig ger of pin io4 is disabled. io4-inen = 1 input schmitt trig ger of pin io4 is enabled. io3-inen input enable for prog rammable i/o pin io3 io3-inen = 0 input schmitt trig ger of pin io3 is disabled. io3-inen = 1 input schmitt trig ger of pin io3 is enabled. io2-inen input enable for prog rammable i/o pin io2 io2-inen = 0 input schmitt trig ger of pin io2 is disabled. io2-inen = 1 input schmitt trig ger of pin io2 is enabled. io1-inen input enable for prog rammable i/o pin io1 io1-inen = 0 input schmitt trig ger of pin io1 is disabled. io1-inen = 1 input schmitt trig ger of pin io1 is enabled. io4-m mask bit for io4-du bit io4-m = 0 each change of the io 4 bit generates an interrupt. io4-m = 1 changes of the io4 bi t do not generate interrupts. io3-m mask bit for io3-du bit io3-m = 0 each change of the io 3 bit generates an interrupt. io3-m = 1 changes of the io3 bi t do not generate interrupts.
duslic preliminary data sheet 283 ds3, 2003-07-11 io2-m mask bit for io2-du bit io2-m = 0 each change of the io 2 bit generates an interrupt. io2-m = 1 changes of the io2 bi t do not generate interrupts. io1-m mask bit for io1-du bit io1-m = 0 each change of the io 1 bit generates an interrupt. io1-m = 1 changes of the io1 bi t do not generate interrupts.
duslic preliminary data sheet 284 ds3, 2003-07-11 13 h ioctl2 i/o control register 2 00 h y bit 76543210 io[4:1]-oen io[4:1]-dd io4-oen enabling the ou tput driver of pin io4 io4-oen = 0 the output driver of pin io4 is disabled. io4-oen = 1 the output driver of pin io4 is enabled. io3-oen enabling the ou tput driver of pin io3 io3-oen = 0 the output driver of pin io3 is disabled. io3-oen = 1 the output driver of pin io3 is enabled. io2-oen enabling the ou tput driver of pin io2 io2-oen = 0 the output driver of pin io2 is disabled. io2-oen = 1 the output driver of pin io2 is enabled. io1-oen enabling the ou tput driver of pin io1 if external ringing is selected (bit r ext-en in register bcr2 set to 1), pin io1 cannot be controlled by the user but is utilized by the slicofi-2s to control the ring relay. io1-oen = 0 the output driver of pin io1 is disabled. io1-oen = 1 the output driver of pin io1 is enabled. io4-dd value for the programmable i/o pin io4 if programmed as an output pin. io4-dd = 0 the corresponding pi n is driving a logical 0. io4-dd = 1 the corresponding pi n is driving a logical 1. io3-dd value for the programmable i/o pin io3 if programmed as an output pin. io3-dd = 0 the corresponding pi n is driving a logical 0. io3-dd = 1 the corresponding pi n is driving a logical 1.
duslic preliminary data sheet 285 ds3, 2003-07-11 io2-dd value for the programmable i/o pin io2 if programmed as an output pin. io2-dd = 0 the corresponding pi n is driving a logical 0. io2-dd = 1 the corresponding pi n is driving a logical 1. io1-dd value for the programmable i/o pin io1 if programmed as an output pin. io1-dd = 0 the corresponding pi n is driving a logical 0. io1-dd = 1 the corresponding pi n is driving a logical 1.
duslic preliminary data sheet 286 ds3, 2003-07-11 14 h ioctl3 i/o control register 3 94 h y bit 76543210 dup[3:0] dup-io[3:0] dup[3:0] data upstream persistence counte r end value. restricts the rate of interrupts generated by the hook bit in the interrupt register intreg1. the interval is programmable from 1 to 16 ms in steps of 1 ms (reset value is 10 ms). the dup[3:0] valu e affects the blocking period for ground key detection (see chapter 2.6 ). dup-io[3:0] data upstream persistenc e counter end value for the i/o pins when used as digital input pins. the bits icon and vtrlim in register intreg1. the interval is programmable from 0.5 to 60.5 ms in steps of 4 ms (reset value is 16.5 ms). dup[3:0] hook active, ringing hook power down gndk gndk f min,acsup 1) 1) minimum frequency for ac suppression. 0000 1 2 ms 4 ms 125 hz 0001 2 4 ms 8 ms 62.5 hz ... 1111 16 32 ms 64 ms 7.8125 hz
duslic preliminary data sheet 287 ds3, 2003-07-11 15 h bcr1 basic configuration register 1 00 h y bit 7 6 5 4 3210 hir hit 0 revpol actr actl sel-slic[1:0] hir this bit modifies different basic mo des. in ringing mode, an unbalanced ringing on the ring-wire (ror) is enabled. in acti ve mode, high impedance on the ring-wire is performed (hir). it enables the hirt-mode, together with the hit bit. hir = 0 normal operation (ringing mode). hir = 1 controls slic-s/-s2-interfa ce and sets the ring wire to high impedance (active mode). hit this bit modifies different basic mode s. in ringing mode, an unbalanced ringing on the tip-wire (rot) is enab led. in active m ode, high impedance on the tip-wire is perfor med (hit). it enables the hirt-mode, together with the hir bit. hit = 0 normal operat ion (ringing mode). hit = 1 controls slic-s/-s2-interfa ce and sets the tip-wire to high impedance (active mode). revpol reverse polarity of dc feeding revpol = 0 normal polarity. revpol = 1 reverse polarity. actr selection of extended battery feeding in active mode. in this case v hr ? v bath for slic-s/-s2 is used. actr = 0 no extended batt ery feeding selected. actr = 1 extended batt ery feeding selected.
duslic preliminary data sheet 288 ds3, 2003-07-11 actl selection of the low battery supply voltage v batl on slic-s/-s2 if available. valid only in active mo de of the slicofi-2s. actl = 0 low battery supply voltage on slic-s/-s2 is not selected. actl = 1 low battery supply volt age on slic-s/-s2 is selected. sel-slic[1:0] selection of the current slic type used. for sl ic-e/-e2 and slic-p, the appropriate predefined mode table has to be selected. sel-slic[1:0] = 0 0 slic-e/-e2 selected. sel-slic[1:0] = 0 1 slic-p selected. sel-slic[1:0] = 1 0 slic-p selected for extremely power sensitive applications using external ringing. sel-slic[1:0] = 1 1 reserved for future use.
duslic preliminary data sheet 289 ds3, 2003-07-11 for slic-p two select ions are possible. the standard slic-p selection automatically uses the io2 pin of the slicofi-2 to control the c3 pi n of the slic-p. by using pin c3 as well as the pins c1 and c2, all possible operati ng modes of the slic-p can be selected. for slic-p 1.2 only the operating modes with 90 ma current limitation can be selected (actl90, acth90, actr90). note: if with slic-p v1.2 the 60 ma current limitation modes (actl60, acth60, actr60) ar e to be used, then the slic type sel-slic[1:0] = 10 has to be programmed. in this case the c3 pin of the slic-p v1.2 can al so be controlled by the io2 pin of the slicofi-2. however, the io2 pin has then to be programmed manually by the user according to the slic-p v1.2 interface code table. for extremely power sensitive appl ications using external ringing with slic-p sel-slic[1:0] = 10 shou ld be chosen. in this case, internal unbalanced ringing is not needed and therefore there is no need to switch the c3 pi n of the slic-p to 'hi gh'. the c3 pin of the slic-p must be connected to gnd and the io2 pin of the slicofi-2 is programmable by the user. there is no need for a high battery voltage fo r ringing either. this mode uses v batr for the on-hook voltage (e.g. ?48 v) in power down resistive (pdr) mode and t he other battery supply voltages (e.g. v bath = ?24 v and v batl = ?18 v) can be used for the off-hook state. this wi ll help to save po wer because the lowest possible battery voltage can be se lected (see duslic voltage and power application note).
duslic preliminary data sheet 290 ds3, 2003-07-11 1) only for duslic-s, is set to 1 for duslic-s2 2) only for duslic-s, is set to 0 for duslic-s2 16 h bcr2 basic configuration register 2 00 h y bit 76543210 rext- en soft- dis ttx- dis 1) ttx- 12k 2) him-an ac- xgain 0pdot- dis rext-en enables the use of an ex ternal ring-signa l generator. the synchronization is done via the rsync pin and the ri ng-burst-enable signal is transferred via the io1 pin. rext-en = 0 external ringing is disabled. rext-en = 1 external ringing enabled. soft-dis polarity soft reversal (to mi nimize noise on dc feeding) soft-dis = 0 polarity so ft reversal active. soft-dis = 1 polarity hard reversal. ttx-dis disables the generation of ttx bursts for metering signals. if they are disabled, reverse polarity is used instead. ttx-dis = 0 ttx bursts are enabled. ttx-dis = 1 ttx bursts are dis abled, reverse polarity used. ttx-12k selection of ttx frequencies ttx-12k = 0 selects 16 khz ttx si gnals instead of 12 khz signals. ttx-12k = 1 12 khz ttx signals.
duslic preliminary data sheet 291 ds3, 2003-07-11 him-an higher impedance in analog impedance matching loop. the value of this bit must correspo nd to the select ion done in the duslicos tool when calcul ating the coefficients. if the coefficients are calculated with standard impedance in analog impedance matching loop, him-an must be set to 0; if the coefficients are calculated with high impedance in analog impedance matching loop, him-an must be set to 1. him-an = 0 standard impedance in analog impedance matching loop him-an = 1 high impedance in an alog impedance matching loop ac-xgain analog gain in transmit dire ction (should be set to zero). ac-xgain = 0 no addit ional analog gai n in transmit direction. ac-xgain = 1 additional 6 db anal og amplification in transmit direction. pdot-dis power down overtemperature disable pdot-dis = 0 when overtemperatur e is detected, the slic-s/-s2 is automatically switched into power down high impedance mode (pdh). this is the safe operation mode for the slic-s/-s2 in case of overtemperature. to leave the automatica lly activated pdh mode, duslic must be switched manually to pdh mode and then in the mode as desired. pdot-dis = 1 when overtemperatur e is detected, the slic-s/-s2 does not automatically swit ch into power down high impedance mode. in this ca se, the output current of the slic-s/-s2 buffers is limited to a value which keeps the slic-s/-s2 temp erature below the upper temperature limit.
duslic preliminary data sheet 292 ds3, 2003-07-11 17 h bcr3 basic configuration register 3 00 h y bit 76 5 43210 mu- law lin 0 pcmx- en 0 0 0 cram- en mu-law selects the pcm law mu-law = 0 a-l aw enabled. mu-law = 1 -law enabled. lin voice transmission in a 16-bit linea r representation for test purposes. note: voice transmission on the other channel is inhibited if one channel is set to linear m ode and the iom-2 interface is used. in pcm/microcontroller interfac e mode, both channels can be in linear mode using two consecutiv e pcm timeslots on the highways. a proper timeslot select ion must be specified. lin = 0 pcm mode enabled (8 bit, a-law, or -law). lin = 1 linear mode enabled (16 bit). pcmx-en enables writing of subscriber voice data to the pcm highway. pcmx-en = 0 writing of subscriber voice data to pcm highway is disabled. pcmx-en = 1 writing of subscriber voice data to pcm highway is enabled. cram-en coefficients from cram are used fo r programmable filters and dc loop behavior. cram-en = 0 coefficients from rom are used. cram-en = 1 coefficients from cram are used.
duslic preliminary data sheet 293 ds3, 2003-07-11 18 h bcr4 basic configuration register 4 00 h y bit 76543210 th-dis im-dis ax-dis ar-dis frx- dis frr- dis hpx- dis hpr- dis th-dis disables the th filter. th-dis = 0 th filter is enabled. th-dis = 1 th filt er is disabled (h th = 0). im-dis disables the im filter. im-dis = 0 im filter is enabled. im-dis = 1 im filter is disabled (h im = 0). ax-dis disables the ax filter. ax-dis = 0 ax filt er is enabled. ax-dis = 1 ax filter is disabled (h ax = 1). ar-dis disables the ar filter. ax-dis = 0 ar filter is enabled. ax-dis = 1 ar filter is disabled (h ar = 1). frx-dis disables the frx filter. frx-dis = 0 frx filter is enabled. frx-dis = 1 frx filter is disabled (h frx = 1). frr-dis disables the frr filter. frr-dis = 0 frr filter is enabled. frr-dis = 1 frr filter is disabled (h frr = 1). hpx-dis disables the high-pass filt er in transmit direction. hpx-dis = 0 high-pass filter is enabled. hpx-dis = 1 high-pass fi lter is disabled (h hpx = 1).
duslic preliminary data sheet 294 ds3, 2003-07-11 hpr-dis disables the high-pass filt er in receive direction. hpr-dis = 0 high-pass filter is enabled. hpr-dis = 1 high-pass filter is disabled (h hpr = 1). 19 h reserved 00 h y bit 76543210 00000000
duslic preliminary data sheet 295 ds3, 2003-07-11 1a h dscr dtmf sender configuration register 00 h y bit 76543210 dg-key[3:0] cor8 ptg tg2-en tg1-en dg-key[3:0] selects one of sixteen dtmf keys generated by the 2 tone generators. the key will be generated if both tg1-en and tg2-en are 1. table 71 dtmf keys f low [hz] f high [hz] digit dg-key3 dg -key2 dg-key1 dg-key0 697120910001 697133620010 697147730011 770120940100 770133650101 770147760110 852120970111 852133681000 852147791001 941133601010 941 1209 * 1 0 1 1 9411477#1100 697 1633 a 1 1 0 1 770 1633 b 1 1 1 0 852 1633 c 1 1 1 1 941 1633 d 0 0 0 0 cor8 cuts off the receive path at 8 khz be fore the tone generat or summation point. allows sending of tone generator signals without overlaid voice. cor8 = 0 cut off receive path disabled. cor8 = 1 cut off receive path enabled.
duslic preliminary data sheet 296 ds3, 2003-07-11 ptg programmable coefficients for to ne generators will be used. ptg = 0 frequencies set by dg -key are used fo r both tone generators. tone generator tg1 level: ?5 dbm0 tone generator tg2 level: ?3 dbm0 ptg = 1 cram coefficients used for both tone generators. tone generator tg1 and tg 2 frequencies and levels can be programmed in th e duslicos dc control parameters 3/4. the levels are set in dbm0: level[dbm] = level[dbm0] + l r [dbr] tg2-en enables tone generator two tg2-en = 0 tone gene rator is disabled. tg2-en = 1 tone gene rator is enabled. tg1-en enables tone generator one tg1-en = 0 tone generator is disabled. tg1-en = 1 tone gene rator is enabled. 1b h reserved 00 h y bit 76543210 00000000
duslic preliminary data sheet 297 ds3, 2003-07-11 1c h lmcr1 level metering config uration register 1 22 h y bit 7 6 5 4 3 2 1 0 test- en lm-en lm- thm pcm2dc lm2 pcm lm- once lm- mask dc- ad16 test-en activates the slicofi-2s test features controlled by test registers tstr1 to tstr5. test-en = 0 slicofi-2s test features are disabled. test-en = 1 slicofi-2s test features are enabled. note: the test register bits can be programmed before the test-en bit is set to 1. lm-en enables level metering. a positive transitio n of this bit starts level metering (ac and dc). lm-en = 0 level metering stops. lm-en = 1 level metering enabled. lm-thm level metering threshold mask bit lm-thm = 0 a change of the lm -thres bit (register intreg2) generates an interrupt. lm-thm = 1 no interrupt is generated. pcm2dc pcm voice channel data added to the dc-output. pcm2dc = 0 no rmal operation. pcm2dc = 1 pcm voice channel data is added to dc output. lm2pcm level metering source/result (dependi ng on lm-en bit) feeding to pcm or iom-2 interface. lm2pcm = 0 normal operation. lm2pcm = 1 level metering so urce/result is fed to the pcm or iom-2 interface. lm-once level metering execution mode.
duslic preliminary data sheet 298 ds3, 2003-07-11 lm-once = 0 level metering is executed continuously. lm-once = 1 level metering is exec uted only once. to start the level meter again, the lm-e n bit must again be set from 0 to 1. lm-mask interrupt masking for level metering. lm-mask = 0 an interrupt is g enerated after level metering. lm-mask = 1 no interrupt is generated. dc-ad16 additional digital amplif ication in the dc ad path for level metering. dc-ad16 = 0 additional gain factor 16 disabled. dc-ad16 = 1 additional ga in factor 16 enabled.
duslic preliminary data sheet 299 ds3, 2003-07-11 1d h lmcr2 level metering config uration register 2 00 h y bit 76543210 lm- notch lm- filt lm- rect ramp- en lm-sel[3:0] lm-notch selection of a notch filt er instead of the band -pass filter for level metering. lm-notch = 0 notch filter selected. lm-notch = 1 band-pa ss filter selected. lm-filt enabling of a programm able band-pass or notch filter for level metering. lm-filt = 0 normal operation. lm-filt = 1 band-pass/ notch filter enabled. lm-rect rectifier in dc level meter lm-rect = 0 rectifier disabled. lm-rect = 1 rectifier enabled. ramp-en the ramp generator wor ks together with the rng-offset bits in lmcr3 and the lm-en bit to create di fferent voltage slopes in the dc- path. ramp-en = 0 ramp generator disabled. ramp-en = 1 ramp generator enabled. lm-sel[3:0] selection of the source for the level metering. lm-sel[3:0] = 0 0 0 0 ac level metering in transmit lm-sel[3:0] = 0 0 0 1 real part of ttx (ttx real ) lm-sel[3:0] = 0 0 1 0 imaginary part of ttx (ttx img ) lm-sel[3:0] = 0 0 1 1 not used lm-sel[3:0] = 0 1 0 0 dc out voltage on dcn-dcp lm-sel[3:0] = 0 1 0 1 dc current on it lm-sel[3:0] = 0 1 1 0 ac level metering in receive
duslic preliminary data sheet 300 ds3, 2003-07-11 lm-sel[3:0] = 0 1 1 1 ac level me tering in receive and transmit lm-sel[3:0] = 1 0 0 0 not used lm-sel[3:0] = 1 0 0 1 dc current on il lm-sel[3:0] = 1 0 1 0 voltage on io3 lm-sel[3:0] = 1 0 1 1 voltage on io4 lm-sel[3:0] = 1 1 0 0 not used lm-sel[3:0] = 1 1 0 1 v dd lm-sel[3:0] = 1 1 1 0 offset of dc-p refi (short circuit on dc-prefi input) lm-sel[3:0] = 1 1 1 1 voltage on io4 ? io3
duslic preliminary data sheet 301 ds3, 2003-07-11 1e h lmcr3 level metering config uration register 3 00 h y bit 76543210 ac- short -en rtr- sel lm-itime[3:0] rng- offset[1:0] ac-short-en the input pin itac will be set to a lower input impedan ce so that the capacitor c itac can be recharged faster during a soft reversal which makes it more silent during conversation. ac-short-en = 0 input impedance of the itac pin is standard. ac-short-en = 1 input impedance of the itac pin is lowered. rtr-sel ring trip method selection. rtr-sel = 0 ring trip with a dc offset is selected. rtr-sel = 1 ac ring trip is selected. recommended for short lines only. lm-itime[3:0] integration time for ac level metering. lm-itime[3:0] = 0 0 0 0 16 ms lm-itime[3:0] = 0 0 0 1 2 16 ms lm-itime[3:0] = 0 0 1 0 3 16 ms ? lm-itime[3:0] = 1 1 1 1 16 16 ms rng- offset[1:0] selection of the ri ng offset source.
duslic preliminary data sheet 302 ds3, 2003-07-11 by setting the ramp-en bit to 1, the ramp generator is star ted by setting lm-en from 0 to 1 (see figure 68 ). exception: transition of rng-offset from 10 to 11 or 11 to 10 where the ramp generator is started automatically (see figure 68 ). for ring offset ro1, the usual ?hook threshol d ring? is used. using ring offset ro2 or ro3 in any ringing mode (r inging and ring paus e) also changes t he hook thresholds. in this case the ?hook message waiting? threshold is used automatically. when using the ring offsets ro2 and ro3 for message wa iting, an additional lamp current is expected. in this case, the hook message waiting threshold should be programmed higher than the hook threshold ring. ook threshold ring. rng- offset[1:0] ring offset voltage in given mode active acth actl active ring actr ring pause ringing 0 0 voltage given by dc regulation voltage given by dc regulation ring offset ro1 hook threshold ring 0 1 ring offset ro1/2 (no dc regulation) ring offset ro1 (no dc regulation) ring offset ro1 hook threshold ring 1 0 ring offset ro2/2 (no dc regulation) ring offset ro2 (no dc regulation) ring offset ro2 hook message waiting 1 1 ring offset ro3/2 (no dc regulation) ring offset ro3 (no dc regulation) ring offset ro3 hook message waiting
duslic preliminary data sheet 303 ds3, 2003-07-11 figure 68 example for switching betw een different ring offset voltages the three programmable ring off sets are typically used fo r the following purposes: besides the typical usage described in table 72 , the ring offsets ro1, ro2, and ro3 can also be used for the generation of different custom waveforms (see figure 68 ). table 72 typical usage for the three ring offsets ring offset voltage application ring offset ro1 ringing ring offset ro2 low volta ge for message waiting lamp ring offset ro3 high volt age for message waiting lamp 10 11 rng-offset[1:0] ramp-en (register lmcr2) lm-en (register lmcr1) generated ring offset (ro) voltage t ro1 = 20 v ro2 = 40 v ro3 = 120 v 01 01 ezm35002
duslic preliminary data sheet 304 ds3, 2003-07-11 1f h ofr1 offset register 1 (high byte) 00 h y bit 76543210 offset-h[7:0] offset-h[7:0] offset register high byte. 20 h ofr2 offset register 2 (low byte) 00 h y bit76543210 offset-l[7:0] offset-l[7:0] offset register low byte. the value of this regist er together with off set-h is added to the input of the dc loop to compensate a given offset of the current sensors in the slic-s/-s2.
duslic preliminary data sheet 305 ds3, 2003-07-11 21 h pcmr1 pcm receive register 1 00 h y bit 76543210 r1- hw r1-ts[6:0] r1-hw selection of the pcm high way for receiving pcm data or the higher byte of the first data sample if lin ear 16 khz pcm mode is selected. r1-hw = 0 pcm highway a is selected. r1-hw = 1 pcm highway b is selected. r1-ts[6:0] selection of the pcm timeslot used for data reception. note: the programmed pcm timeslot mu st correspond to the available slots defined by the pc lk frequency. no recept ion will occur if a slot outside the actual numbers of slots is programmed. in linear mode (bit lin = 1 in register bcr3 ) r1-ts defines th e first of two consecutive slots used for reception.
duslic preliminary data sheet 306 ds3, 2003-07-11 22 h reserved 00 h y bit 76543210 23 h reserved 00 h y bit 76543210 24 h reserved 00 h y bit 76543210
duslic preliminary data sheet 307 ds3, 2003-07-11 25 h pcmx1 pcm transmit register 1 00 h y bit 76543210 x1-hw x1-ts[6:0] x1-hw selection of the pcm hi ghway for transmitting pc m data or the higher byte of the first data sample if linear 16 khz pcm mo de is selected. x1-hw = 0 pcm highwa y a is selected. x1-hw = 1 pcm highwa y b is selected. x1-ts[6:0] selection of the pcm timeslot used for data transmission. note: the programmed pcm timeslot mu st correspond to the available slots defined by the pc lk frequency. no transmission will occur if a slot outside the actual numbers of slots is prog rammed. in linear mode, x1-ts defines the first of two consecutive slots used for transmission. pcm data transmission is controlled by bits 6 to 2 in register bcr3.
duslic preliminary data sheet 308 ds3, 2003-07-11 26 h reserved 00 h y bit 76543210 27 h reserved 00 h y bit 76543210 28 h reserved 00 h y bit 76543210
duslic preliminary data sheet 309 ds3, 2003-07-11 register setting is active only if bit test-en in register lmcr1 is set to 1. 29 h tstr1 test register 1 00 h ty bit 76543210 pd-ac- pr pd-ac- po pd-ac- ad pd-ac- da pd-ac- gn pd- gnkc pd- ofhc pd- ovtc pd-ac-pr ac-prefi power down pd-ac-pr = 0 normal operation. pd-ac-pr = 1 power down mode. pd-ac-po ac-pofi power down pd-ac-po = 0 normal operation. pd-ac-po = 1 power down mode. pd-ac-ad ac-adc power down pd-ac-ad = 0 normal operation. pd-ac-ad = 1 power down mode, transmit path is inactive. pd-ac-da ac-dac power down pd-ac-da = 0 normal operation. pd-ac-da = 1 power down mode , receive path is inactive. pd-ac-gn ac-gain power down pd-ac-gn = 0 normal operation. pd-ac-gn = 1 power down mode. pd-gnkc ground key comparator (gnk c) is set to power down pd-gnkc = 0 normal operation. pd-gnkc = 1 power down mode.
duslic preliminary data sheet 310 ds3, 2003-07-11 pd-ofhc off-hook comparator (ofhc) power down pd-ofhc = 0 normal operation. pd-ofhc = 1 power down mode. pd-ovtc overtemperature comparator (ovtc) power down pd-ovtc = 0 normal operation. pd-ovtc = 1 power down mode.
duslic preliminary data sheet 311 ds3, 2003-07-11 1) only for duslic-s; for duslic-s2, is set to 0. register setting is active only if bit test-en in register lmcr1 is set to 1. 2a h tstr2 test register 2 00 h ty bit 76543210 pd-dc- pr 0pd-dc- ad pd-dc- da pd- dcbuf 0pd- ttx-a 1) pd-hvi pd-dc-pr dc-prefi power down pd-dc-pr = 0 normal operation. pd-dc-pr = 1 pow er down mode. pd-dc-ad dc-adc power down pd-dc-ad = 0 normal operation. pd-dc-ad = 1 power do wn mode, transmit path is inactive. pd-dc-da dc-dac power down pd-dc-da = 0 normal operation. pd-dc-da = 1 power down mode, receive path is inactive. pd-dcbuf dc-buffer power down pd-dcbuf = 0 normal operation. pd-dcbuf = 1 power down mode. pd-ttx-a ttx adaptation dac an d pofi power down pd-ttx-a = 0 normal operation. pd-ttx-a = 1 power down mode. pd-hvi hv interface (to slic-s/-s2) power down pd-hvi = 0 normal operation. pd-hvi = 1 power down mode.
duslic preliminary data sheet 312 ds3, 2003-07-11 register setting is active only if bit test-en in register lmcr1 is set to 1. 2b h tstr3 test register 3 00 h ty bit 76543210 00ac- dlb- 4m ac- dlb- 128k ac- dlb- 32k ac- dlb- 8k 00 ac-dlb-4m ac digital loop via 4 mh z bitstream. (the loop encloses all digital hardware in the ac path. together wi th dlb-dc, a pure digital test is possible because there is no infl uence of the analog hardware.) ac-dlb-4m = 0 normal operation. ac-dlb-4m = 1 digital loop closed. ac-dlb-128k ac digital loop via 128 khz ac-dlb-128k = 0 normal operation. ac-dlb-128k = 1 digital loop closed. ac-dlb-32k ac digital loop via 32 khz ac-dlb-32k = 0 normal operation. ac-dlb-32k = 1 digital loop closed. ac-dlb-8k ac digital lo op via 8 khz ac-dlb-8k = 0 normal operation. ac-dlb-8k = 1 digital loop closed.
duslic preliminary data sheet 313 ds3, 2003-07-11 register setting is active only if bit test-en in register lmcr1 is set to 1. 2c h tstr4 test register 4 00 h ty bit 76543210 opim- an opim- 4m cor-64 cox-16 0 0 0 0 opim-an open impedance matching loop in the analog part. opim-an = 0 normal operation. opim-an = 1 loop opened. opim-4m open fast digital impedance matching loop in the ha rdware filters. opim-4m = 0 normal operation. opim-4m = 1 loop opened. cor-64 cut off the ac receive path at 64 khz (just before the im filter). cor-64 = 0 normal operation. cor-64 = 1 receive path is cut off. cox-16 cut off the ac transmit pa th at 16 khz. (the th filters can be tested without the influence of the analog part.) cox-16 = 0 normal operation. cox-16 = 1 transmit path is cut off.
duslic preliminary data sheet 314 ds3, 2003-07-11 register setting is only active if bit test-en in register lmcr1 is set to 1. 2d h tstr5 test register 5 00 h ty bit 76543210 000dc- pofi- hi dc- hold 000 dc-pofi-hi dc post filter limit frequency higher value dc-pofi-hi = 0 limit frequency is set to 100 hz (normal operation). dc-pofi-hi = 1 limit frequency is set to 300 hz. dc-hold actual dc output value hol d (value of the last d sp filter stage will be kept) dc-hold = 0 normal operation. dc-hold = 1 dc ou tput value hold.
duslic preliminary data sheet 315 ds3, 2003-07-11 5.3.2 cop command the coefficient operation (cop) command gi ves access to the cram data of the dsps. it is organized in the same way as the sop command. the offset value allows a direct as well as a block access to the cram. writ ing beyond the allowed of fset will be ignored, reading beyond it will give unpr edictable results. the value of a specific cram coefficien t is calculated by th e duslicos software. attention: to ensure proper functionality, it is essenti al that all unused register bits have to be filled with zeros. bit 76543210 byte 1 rd 1 adr[2:0] 1 0 1 byte 2 offset[7:0] rd read data rd = 0 write data to chip. rd = 1 read data from chip. adr[2:0] channel address for the subsequent data adr[2:0] = 0 0 0 channel a adr[2:0] = 0 0 1 channel b (other codes reserv ed for future use)
duslic preliminary data sheet 316 ds3, 2003-07-11 cram coefficients are enabled by setting bit cram-en in re gister bcr3 to 1, except
duslic preliminary data sheet 317 ds3, 2003-07-11 offset [7:0] short name long name 00 h th1 transhybrid filter coefficients part 1 08 h th2 transhybrid filter coefficients part 2 10 h th3 transhybrid filter coefficients part 3 18 h frr frequency-response filter co efficients receive direction 20 h frx frequency-response filter co efficients transmit direction 28 h ar amplification/attenuation stage coefficients receive 30 h ax amplification/attenuation stage coefficients transmit 38 h ptg1 tone generator 1 coefficients 40 h ptg2 tone generator 2 coefficients 48 h lpr low pass filter coefficients receive 50 h lpx low pass filter coefficients transmit 58 h ttx teletax coefficients 60 h im1 impedance matching filt er coefficients part 1 68 h im2 impedance matching filt er coefficients part 2 70 h ringf ringer frequency and amplit ude coefficients (dc loop) 78 h rampf ramp generator coefficients (dc loop) 80 h dcf dc-characteristics coefficients (dc loop) 88 h hf hook threshold c oefficients (dc loop) 90 h tpf low pass filter coefficients (dc loop) 98 h reserved
duslic preliminary data sheet 318 ds3, 2003-07-11 coefficients ptg1 and ptg2 1) which are enabled by setting bit ptg in register dscr to 1. table 73 cram coefficients byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 offset [7:0] transhybrid coefficient part 1 00 h th1 transhybrid coefficient part 2 08 h th2 transhybrid coefficient part 3 10 h th3 fir filter in receive direction 18 h frr fir filter in transmit direction 20 h frx 2nd gain stage receive 1st gain stage receive 28 h ar 2nd gain stage transmit 1st gain stage transmit 30 h ax tg1 band-pass tg1 gain tg1 frequency 38 h ptg1 1) tg2 band-pass tg2 gain tg2 frequency 40 h ptg2 1) reserved 48 h reserved 50 h fir filter for ttx ttx slope ttx level 58 h ttx im k factor im fir filter 60 h im1_f im 4 mhz filter im wdf filter 68 h im2_f ring generator amplitude ring generator frequency ring generator lowpass ring offset ro1 70 h ringf extended battery feeding gain soft reversal end constant ramp cr soft ramp ss ring delay rd 78 h rampf res. in resistive zone r k12 res. in constant current zone r i constant current i k1 knee voltage v k1 open circuit volt. v lim 80 h dcf hook message waiting hook threshold ac ring trip hook threshold ring hook threshold active hook threshold power down 88 h hf voltage level v tr dc lowpass filter tp2 dc lowpass filter tp1 90 h tpf reserved 98 h 16151413121110987654321
duslic preliminary data sheet 319 ds3, 2003-07-11 5.3.2.1 cram programming ranges table 74 cram programming ranges parameter programming range constant current i k1 0...50 ma, ? <0.5ma hook message waiting, hook thresholds 0..25 ma, ? <0.7ma 25...50 ma, ? <1.3ma ring generator frequency f ring 3..40 hz, ? <1hz 40..80 hz, ? <2hz > 80 hz, ? <4hz ring generator amplitude 0..20 v, ? <1.7v 20..85 v, ? <0.9v ring offset ro1 0..25 v, ? <0.6v 25..50 v, ? <1.2v 50..100 v, ? <2.4v, max. 150v knee voltage v k1 , open circuit voltge v lim 0..25 v, ? <0.6v 25..50 v, ? <1.2v >50v, ? <2.4v resistance in resistive zone r k12 0..1000 ? , ? <30 ? resistance in constant current zone r i 1.8 k ? ..4.8 k ? , ? <120 ? 4.8 k ? ..9.6 k ? , ? <240 ? 9.6 k ? ..19 k ? , ? <480 ? 19 k ? ..38 k ? , ? < 960 ? , max. 40 k ?
duslic preliminary data sheet 320 ds3, 2003-07-11 5.3.3 iom-2 interface command/indication byte the command/indication (c/i) channel is used to comm unicate real time status information and for fast control of the duslic . data on the c/i ch annel are continuously transmitted in each frame until new data are sent. data downstream c/i ? channe l byte (recei ve) ? iom-cidd the first six cidd data bits control the general operati ng modes for both duslic channels. according to the io m-2 specification, new data must be present for at least two frames to be accepted. ) table 75 m2, m1, m0: ge neral operating mode cidd slicofi-2s operating mode (for details see ?overview of all duslic operating modes? on page 74 ) m2 m1 m0 1 1 1 sleep, power down (pdrx) 0 0 0 power down high impedance (pdh) 0 10any active mode 1 0 1 ringing (actr burst on) 1 1 0 active with metering 1 00ground start 0 01ring pause cidd data downstream c/i ? channel byte n bit 76543210 m2a m1a m0a m2b m1b m0b mr mx m2a, m1a, m0a select operating mode for duslic channel a m2b, m1b, m0b select operating mode for duslic channel b mr, mx handshake bits monito r receive and transmit (see ?iom-2 interface monitor tr ansfer protocol? on page 133 )
duslic preliminary data sheet 321 ds3, 2003-07-11 data upstream c/i ? channe l byte (transmit) ? iom-cidu this byte is used to quickl y transfer the most important an d time-critical information from the duslic. each transfer fr om the duslic lasts for at least two consecutive frames. cidu data upstream c/ i ? channel byte 00 h n bit 7 6 5 4 3 2 1 0 int-cha hooka gndka int -chb hookb gndkb mr mx int-cha interrupt information channel a int-cha = 0 no interru pt in channel a int-cha = 1 interrupt in channel a hooka hook informati on channel a hooka = 0 on-hook channel a hooka = 1 off-hook channel a gndka ground key inform ation channel a gndka = 0 no longitudin al current detected gndka = 1 longitudi nal current detect ed in channel a int-chb interrupt information channel b int-chb = 0 no interru pt in channel b int-chb = 1 interrupt in channel b hookb hook informati on channel b hookb = 0 on-hook channel b hookb = 1 off-hook channel b gndkb ground key inform ation channel b gndkb = 0 no longitudin al current detected gndkb = 1 longitudi nal current detect ed in channel b mr, mx handshake bits monitor receive and transmit (see ?iom-2 interface monitor tr ansfer protocol? on page 133 )
duslic preliminary data sheet 322 ds3, 2003-07-11 5.3.4 programming examples of the slicofi-2s 5.3.4.1 microcontroller interface sop write to channel 0 starting after th e channel-specific read-only registers 01000100 first command byte (sop write for channel 0) 00010101 second command byte (offset to bcr1 register) 00000000 contents of bcr1 register 00000000 contents of bcr2 register 00010001 contents of bcr3 register 00000000 contents of bcr4 register 00000000 contents of bcr5 register figure 69 waveform of programming example sop write to channel 0 sop read from channel 1 readi ng out the interrupt registers 11001100 first command byte (s op read for channel 1). 00000111 second command byte (offset to interrupt register 1). the slicofi-2s will send data when it has completely re ceived the second command byte. 11111111 dump byte (this byte is always ff h ). 11000000 interrupt register intreg1 (an inte rrupt has occurred, off-hook was detected). 00000010 interrupt register intreg2 (i/o pin 2 is 1). 00000000 interrupt register intreg3 00000000 interrupt register intreg4 figure 70 waveform of programming e xample sop read from channel 0 command offset bcr1 din dclk cs bcr2 bcr3 bcr4 bcr5 ezm220121 ezm220122 dclk cs command offset dump intreg 1 dout din intreg 2 intreg 3 intreg 4
duslic preliminary data sheet 323 ds3, 2003-07-11 5.3.4.2 iom-2 interface an example with the same pr ogramming sequence as before, using the iom-2 interface is presented here to show th e differences between the micr ocontroller interface and the iom-2 interface. sop write to channel 0 starting after th e channel-specific read-only registers monitor mr/mx monitor mr/mx comment data down data up 10000001 10 11111111 11 iom-2 address first byte 10000001 10 11111111 01 iom-2 address second byte 01000100 11 11111111 01 first command byte (sop write for channel 0) 01000100 10 11111111 11 first command byte second time 00010101 11 11111111 01 second command byte (offset to bcr1 register) 00010101 10 11111111 11 second command byte second time 00000000 11 11111111 01 contents of bcr1 register 00000000 10 11111111 11 contents of bcr1 register second time 00000000 11 11111111 01 contents of bcr2 register 00000000 10 11111111 11 contents of bcr2 register second time 00010001 11 11111111 01 contents of bcr3 register 00010001 10 11111111 11 contents of bcr3 register second time 00000000 11 11111111 01 contents of bcr4 register 00000000 10 11111111 11 contents of bcr4 register second time 11111111 11 11111111 01 no more information (dummy byte) 11111111 11 11111111 11 signaling eom (end of message) by holding mx bit at ?1?. because the slicofi-2s has an open comma nd structure, no fixe d command length is given. the iom-2 handshake pr otocol allows for an infini te length of a data stream; therefore, the host must terminate the da ta transfer by sending an end-of-message signal (eom) to the slicofi-2s . the slicofi-2s will abort the transfer only if the host tries to write or read beyond the allowed maximum offsets gi ven by the different types of commands. each transfer must start with th e slicofi-2s-specifi c iom-2 address (81 h ) and must end with an eom of the handshake bits. app ending a command immediately to its predecessor without an eo m in between is not allowed. when reading interrupt register s, slicofi-2s stops the trans fer after the fourth register in iom-2 mode. this is to prevent some host chips from reading 16 bytes because they cannot terminate the tr ansfer after n bytes.
duslic preliminary data sheet 324 ds3, 2003-07-11 sop-read from channel 1 readi ng out the interrupt registers monitor mr/mx monitor mr/mx comment data down data up 10000001 10 11111111 11 iom-2 address first byte 10000001 10 11111111 01 iom-2 address second byte 11001100 11 11111111 01 first command byte (sop read for channel 1) 11001100 10 11111111 11 first command byte second time 00001000 11 11111111 01 second command byte (offset to interrupt register 1) 00001000 10 11111111 11 second command byte second time 11111111 11 11111111 01 acknowledgement for the second command byte 11111111 11 10000001 10 iom-2 address first byte (answer) 11111111 01 10000001 10 iom-2 address second byte 11111111 01 11000000 11 interrupt register intreg1 11111111 11 11000000 10 interrupt register intreg1 second time 11111111 01 00000010 11 interrupt register intreg2 11111111 11 00000010 10 interrupt register intreg2 second time 11111111 01 00000000 11 interrupt register intreg3 11111111 11 00000000 10 interrupt register intreg3 second time 11111111 01 00000000 11 interrupt register intreg4 11111111 11 00000000 10 interrupt register intreg4 second time 11111111 11 01001101 11 slicofi-2s sends the next register 11111111 11 11111111 11 slicofi-2s aborts transmission
duslic electrical characteristics preliminary data sheet 325 ds3, 2003-07-11 6 electrical characteristics 6.1 ac transmission duslic the target figures in this specification are based on the subscriber linecard requirements. the proper adjustment of the programmable filters (t ranshybrid balancing, impedance matching, frequency-re sponse correction) requires the consideration of the complete analog en vironment of the slicofi-2x device. functionality and performa nce are guaranteed for t a = 0 to 70 c by production testing. extented temperature range operation at ?40 c < t a < 85 c is guaranteed by design, characterization and period ically sampling and testing production devices at the temperature extremes. test conditions t a = ?40 c to 85 c, unless otherwise stated. v ddd = v dda = v ddb = v ddr = v ddpll = 3.3 v 5%; v gnda = v gndb = v gndr = v gndd = v gndpll = 0 v r l > 600 ? ; c l < 10 pf l r = 0 ? ?10 dbr l x = 0 ? +3 dbr f = 1014 hz; 0 dbm0; a-law or -law; figure 71 signal defini tions transmit, receive note: to ensure the stability of the slic output buffer, r stab and c stab must be set to the values r stab =30 ? and c stab 300 pf (1 nf in the test circuit figure 71 ). for electromagnetic compatibility, c stab must be set to the mu ch higher value of c stab =15nf. iom ? -2 pcm 0.775v rms tip ring 20.775v rm s 600 ? transm it (x) 0dbm0 receive (r) 0dbm0 600 ? r stab 30 ? c stab 1n x r r x slic peb 426x slicofi-2x peb 326x r stab 30 ? c stab 1n ezm22018
duslic electrical characteristics preliminary data sheet 326 ds3, 2003-07-11 the 0 dbm0 definitions for receive and transmit are: a 0 dbm0 ac signal in transmi t direction is equivalent to 0.775 vrms (referred to an impedance of 600 ? ). a 0 dbm0 ac signal in receive direction is equivalent to 0.775 v rms (referred to an impedance of 600 ? ). l r = ?10 dbr means: a signal of 0 dbm0 at the digi tal input corresponds to ?10 d bm at the analog interface. l x = +3 dbr means: a signal of 3 dbm at the anal og interface corresponds to 0 dbm0 at the digital output. table 76 ac transmission parameter symbol conditi ons limit values unit min. typ. max. longitudinal current capability ac i ll per active line 30 ? ? marms overload level v tr 300 - 4000 hz 2.3 ? ? vrms transmission perf ormance (2-wire) return loss rl 200 - 3600 hz 26 ? ? db insertion loss (2-wire to 4-wire and 4-wire to 2-wire) gain accuracy ? transmit g x 0 dbm0, 1014 hz ?0.25 ? +0.25 db gain accuracy ? receive g r 0 dbm0, 1014 hz ?0.25 ? +0.25 db gain variation with temperature ?40 ? +85 c ?? ??0.1db
duslic electrical characteristics preliminary data sheet 327 ds3, 2003-07-11 frequency response (see figure 73 and figure 74 ) receive loss frequency variation g raf reference frequency 1014 hz , signal level 0 dbm0, h frr =1 f = 0 - 300 hz ?0.25 ? ? db f = 300 - 400 hz ?0.25 ? 0.9 db f = 400 - 600 hz ?0.25 ? 0.65 db f = 600 - 2400 hz ?0.25 ? 0.25 db f = 2400 - 3000 hz ?0.25 ? 0.45 db f = 3000 - 3400 hz ?0.25 ? 1.4 db f = 3400 - 3600 hz ?0.25 ? ? db transmit loss frequency variation g xaf reference frequency 1014 hz , signal level 0 dbm0, h frx =1 f = 0 - 200 hz 0 ?? db f = 200 - 300 hz ?0.25 ? ? db f = 300 - 400 hz ?0.25 ? 0.9 db f = 400 - 600 hz ?0.25 ? 0.65 db f = 600 - 2400 hz ?0.25 ? 0.25 db f = 2400 - 3000 hz ?0.25 ? 0.45 db f = 3000 - 3400 hz ?0.25 ? 1.4 db f = 3400 - 3600 hz ?0.25 ? ? db table 76 ac transmission (cont?d) parameter symbol conditi ons limit values unit min. typ. max.
duslic electrical characteristics preliminary data sheet 328 ds3, 2003-07-11 gain tracking (see figure 75 and figure 76 ) transmit gain signal level variation g xal sinusoidal test method f = 1014 hz, refere nce level ?10 dbm0 vf x i = ?55 to ?50 dbm0 ?1.4 ? 1.4 db vf x i = ?50 to ?40 dbm0 ?0.5 ? 0.5 db vf x i = ?40 to +3 dbm0 ?0.25 ? 0.25 db receive gain signal level variation g ral sinusoidal test method f = 1014 hz, refere nce level ?10 dbm0 d r 0 = ?55 to ?50 dbm0 ?1.4 ? 1.4 db d r 0 = ?50 to ?40 dbm0 ?0.5 ? 0.5 db d r 0 = ?40 to +3 dbm0 ?0.25 ? 0.25 db balance return loss 300 - 3400 hz 26 ? ? db group delay (see figure 77 ) transmit delay, absolute d xa f = 500 - 2800 hz 400 490 585 s receive delay, absolute d ra f = 500 - 2800 hz 290 380 475 s group delay, receive and transmit, relative to 1500 hz d xr f = 500 - 600 hz ? ? 300 s f = 600 - 1000 hz ? ? 150 s f = 1000 - 2600 hz ? ? 100 s f = 2600 - 2800 hz ? ? 150 s f = 2800 - 3000 hz ? ? 300 s overload compression a/d oc ? ? ? ? ? table 76 ac transmission (cont?d) parameter symbol conditi ons limit values unit min. typ. max.
duslic electrical characteristics preliminary data sheet 329 ds3, 2003-07-11 longitudinal balance (acc ording to itu-t o.9) longitudinal conversion loss l-t 300 - 1000 hz duslic-s/-e/-p duslic-s2/-e2 3400 hz duslic-s/-e/-p duslic-s2/-e2 53 60 52 56 58 65 55 59 ? ? ? ? db db db db input longitudinal interference loss l-4 300 - 1000 hz duslic-s/-e/-p duslic-s2/-e2 3400 hz duslic-s/-e/-p duslic-s2/-e2 53 60 52 56 58 65 55 59 ? ? ? ? db db db db transversal to longitudinal t-l 300 - 4000 hz 46 ? ? db longitudinal signal generation 4-l 300 - 4000 hz 46 ? ? db ttx signal generation ttx signal v ttx at 200 ? ??2.5vrms out-of-band noise (single frequency inband ?25 dbm0) transversal v tr 12 khz - 200 khz ? ?55 ?50 dbm longitudinal v tr 12 khz - 200 khz ? ?55 ?50 dbm out-of-band idle channel noise at analog output measured with 3 khz bandwidth v tr 10 khz ? ? ?50 dbm v tr 300 khz ? ? ?50 dbm v tr 500 khz ? ? ?70 dbm v tr 1000 khz ? ? ?70 dbm table 76 ac transmission (cont?d) parameter symbol conditi ons limit values unit min. typ. max.
duslic electrical characteristics preliminary data sheet 330 ds3, 2003-07-11 out-of-band signals at analog output (receive) (see figure 78 ) out-of-band signals at analog input (transmit) (see figure 79 ) total harmonic distortion 2-wire to 4-wire thd4 ?7 dbm0, 300 - 3400 hz ??50?44db 4-wire to 2-wire thd2 ?7 dbm0, 300 - 3400 hz ??50?44db idle channel noise 2-wire port (receive) a-law n rp psophometric ttx disabled ttx enabled ? ? ? ? ?74 ?70 dbmp dbmp -law n rc c message ttx disabled ttx enabled ? ? ? ? 16 20 dbrnc dbrnc pcm side (transmit) a-law n tp psophometric ttx disabled ttx enabled ? ? ? ? ?69 ?67 dbm0p dbm0p -law n tc c message ttx disabled ttx enabled ? ? ? ? 18 20 dbrnc dbrnc table 76 ac transmission (cont?d) parameter symbol conditi ons limit values unit min. typ. max.
duslic electrical characteristics preliminary data sheet 331 ds3, 2003-07-11 distortion (sinusoidal test method, see figure 81 , figure 80 and figure 82 ) signal to total distortion transmit std x output connection: l x =0dbr f = 1014 hz (c message-weighted for -law, psophometrically weight ed for a-law), ttx-dis = 1 ?45 dbm0 24 ? ? db ?40 dbm0 29 ? ? db ?30 dbm0 35 ? ? db ?20 dbm0 36 ? ? db ?10 dbm0 36 ? ? db 3 dbm0 36 ? ? db signal to total distortion transmit std x output connection: l x =0dbr f = 1014 hz (c message-weighted for -law, psophometrically weight ed for a-law), ttx-dis = 0 ?45 dbm0 23 ? ? db ?40 dbm0 28 ? ? db ?30 dbm0 34 ? ? db ?20 dbm0 36 ? ? db ?10 dbm0 36 ? ? db 3 dbm0 36 ? ? db signal to total distortion receive std r input connection: l r =?7dbr f = 1014 hz (c message-weighted for -law, psophometrically weight ed for a-law), ttx-dis = 1 ?45 dbm0 21 ? ? db ?40 dbm0 26 ? ? db ?30 dbm0 33 ? ? db ?20 dbm0 35.5 ? ? db ?10 dbm0 36 ? ? db 3 dbm0 36 ? ? db table 76 ac transmission (cont?d) parameter symbol conditi ons limit values unit min. typ. max.
duslic electrical characteristics preliminary data sheet 332 ds3, 2003-07-11 signal to total distortion receive std r input connection: l r =?7dbr f = 1014 hz (c message-weighted for -law, psophometrically weight ed for a-law), ttx-dis = 0 ?45 dbm0 19 ? ? db ?40 dbm0 23.5 ? ? db ?30 dbm0 31 ? ? db ?20 dbm0 35.5 ? ? db ?10 dbm0 36 ? ? db 3 dbm0 36 ? ? db signal to total distortion receive std r input connection: l r =0dbr f = 1014 hz (c message-weighted for -law, psophometrically weight ed for a-law), ttx-dis = 1 ?45 dbm0 24 ? ? db ?40 dbm0 29 ? ? db ?30 dbm0 35 ? ? db ?20 dbm0 36 ? ? db ?10 dbm0 36 ? ? db 3 dbm0 36 ? ? db signal to total distortion receive std r input connection: l r =0dbr f = 1014 hz (c message-weighted for -law, psophometrically weight ed for a-law), ttx-dis = 0 ?45 dbm0 23 ? ? db ?40 dbm0 28 ? ? db ?30 dbm0 34 ? ? db ?20 dbm0 36 ? ? db ?10 dbm0 36 ? ? db 3 dbm0 36 ? ? db table 76 ac transmission (cont?d) parameter symbol conditi ons limit values unit min. typ. max.
duslic electrical characteristics preliminary data sheet 333 ds3, 2003-07-11 figure 72 overload compression power supply rejection ratio v dd / v tr (slic) psrr 300 - 3400 hz actl, acth 33 ? ? db v ddi / v tr ( slicofi-2x ) i = a, b, d, r, pll psrr 300 - 3400 hz actl, acth 27 ? ? db v bath / v tr , v batl / v tr (slic) psrr 300 - 3400 hz 33 ? ? db table 76 ac transmission (cont?d) parameter symbol conditi ons limit values unit min. typ. max. 01 2 4 56789 -1 0 2 3 4 5 6 7 8 9 1 0.25 -0.25 3 fundamental input power (dbm0) fundamental output power (dbm0) 3.4 4.2 4.5 ezm14009
duslic electrical characteristics preliminary data sheet 334 ds3, 2003-07-11 6.1.1 frequency response figure 73 frequency response transmit reference frequency 1 khz , signal level 0 dbm0, h frx =1 figure 74 frequency response receive reference frequency 1 khz , signal level 0 dbm0, h frr = 1 1.0 -1 0 1 2 khz frequency db attenuation 3.0 2.0 3.4 0 .3 3.6 .2 .4 .6 2.4 -0.25 0.25 0.45 0.65 0.9 1.4 x ezm00110 1.0 -1 0 1 2 khz frequency db attenuation 3.0 2.0 3.4 0 .3 3.6 .4 .6 2.4 -0.25 0.25 0.45 0.65 0.9 1.4 x ezm00111
duslic electrical characteristics preliminary data sheet 335 ds3, 2003-07-11 6.1.2 gain tracking (receive or transmit) the gain deviations stay within the limits in th e figures below. figure 75 gain tracking receive measured with a sine wave of f = 1014 hz, reference level is ?10 dbm0 figure 76 gain tracking transmit measured with a sine wave of f = 1014 hz, reference level is ?10 dbm0 -70 -60 -55 -50 -40 -30 -20 -10 0 3 10 input level dbm0 + 0.25 + 0.5 + 1 + 1.4 + 2 - 0.25 - 0.5 - 1 - 1.4 - 2 db g ezm00117 -70 -60 -55 -50 -40 -30 -20 -10 0 3 10 input level dbm0 + 0.25 + 0.5 + 1 + 1.4 + 2 - 0.25 - 0.5 - 1 - 1.4 - 2 db g ezm00118
duslic electrical characteristics preliminary data sheet 336 ds3, 2003-07-11 6.1.3 group delay minimum delays occur when bo th frequency response receiv e and transmit filters (bit frr-dis and bit frx-dis in register bcr4 set to 1) are disabled. that includes the delay through a/d and d/a converters. specif ic filter programming may cause additional group delays. absolute gro up delay also depe nds on the progra mmed time slot. group delay distortion stays within the limits in th e figures below. figure 77 group delay distor tion receive and transmit signal level 0 dbm0 6.1.4 out-of-band signals at analog output (receive) with a 0 dbm0 sine wa ve with a frequency of f (300 hz to 3.4 khz) applied to the digital input, the level of any resulting out-of-ba nd signal at the analog outp ut will stay at least x db below a 0 dbm0, 1 khz sine wave re ference signal at the analog output. table 77 group delay absolute values: signal level 0 dbm0 parameter symbol limit values unit test condition fig. min. typ. max. transmit delay d xa 400 490 585 s f = 1.5 khz ? receive delay d ra 290 380 475 s f = 1.5 khz ? 0 0.5 0.6 1 1.5 2 2.6 2.8 3 3.5 4 frequency khz 0 100 150 200 300 400 500 t g s ezm00112
duslic electrical characteristics preliminary data sheet 337 ds3, 2003-07-11 figure 78 out-of-band signals at analog output (receive) itd09762 0 0.06 0.1 3.4 4.0 4.6 6.0 10.0 18.0 200 db 35 30 25 20 15 10 0 receive out-of-band discrimination x 45 28 5 khz f 40 3.4 ... 4.6 khz: x 14 4000 f ? 1200 -------------------- - ?? ?? sin 1 ? ?? ?? ? =
duslic electrical characteristics preliminary data sheet 338 ds3, 2003-07-11 6.1.5 out-of-band signals at analog input (transmit) with a 0 dbm0 out-of-ba nd sine wave signal with a frequency of f (< 100 hz or 3.4 khz to 100 khz) applied to the analog input, the level of any result ing frequency component at the digital output will stay at least x db below a 0 dbm0, 1 khz sine wave reference signal at the analog input. 1) figure 79 out-of-band signals at analog input (transmit) 1) poles at 12 khz 150 hz and 16 khz 150 hz respectively and harmonics will be provided itd09763 3.4 ... 4.0 khz: x 14 4000 f ? 1200 -------------------- - ?? ?? sin 1 ? ?? ?? ? = 4.0 ... 4.6 khz: x 18 4000 f ? 1200 -------------------- - ?? ?? sin 7 9 -- - ? ?? ?? ? = 0 0.06 0.1 3.4 4.0 4.6 6.0 10.0 18.0 100 40 35 32 30 25 20 15 10 0 transmit out-of-band discrimination x khz f db
duslic electrical characteristics preliminary data sheet 339 ds3, 2003-07-11 6.1.6 total distortion measured with sine wave the signal to total distor tion ratio exceeds the limits in the following figure: figure 80 total distortion transmit (l x =0dbr) measured with a sine wave of f = 1014 hz (c message-weighted for -law, psophome- trically weighted for a-law) figure 81 total distortion receive (l r =?7dbr) measured with a sine wave of f = 1014 hz (c message-weighted for -law, psophome- trically weighted for a-law) -60 -50 -40 -30 -20 -10 0 dbm0 d b 40 30 20 10 0 -45 29 input level s/d 24 35 3 36 ttx-dis = 0 ttx-dis = 1 23 28 34 ezm00120 -60 -50 -40 -30 -20 -10 0 dbm0 db 40 30 20 10 0 -45 34 21 input level s/d 36 35,5 3 26 36 19 23.5 31 ttx-dis = 0 ttx-dis = 1 ezm00119
duslic electrical characteristics preliminary data sheet 340 ds3, 2003-07-11 figure 82 total distortion receive (l r =0dbr) measured with a sine wave of f = 1014 hz (c message-weighted for -law, psophome- trically weighted for a-law) -60 -50 -40 -30 -20 -10 0 dbm0 d b 40 30 20 10 0 -45 29 input level s/d 24 35 3 36 ttx-dis = 0 ttx-dis = 1 23 28 34 ezm00120
duslic electrical characteristics preliminary data sheet 341 ds3, 2003-07-11 6.2 dc characteristics t a = ?40 c to 85 c, unless otherwise stated. table 78 dc characteristics parameter symbol conditions limit values unit min. typ. max. line termination tip, ring sinusoidal ringing max. ringing voltage v rng0 v hr ? v bath = 150 v, v dc = 20 v for ring trip (duslic-e/-e2) ? v batr = 150 v, v dc = 20 v for ring trip (duslic-p) v hr ? v bath = 90 v, v dc = 20 v for ring trip (duslic-s/-s2) 85 85 45 ? ? ? ? ? ? vrms vrms vrms output impedance r out slic output buffer and r stab ?61? ? harmonic distortion thd ? ? ? 5 % output current limit | i r, max. |, | i t, max. | modes: active slic-e/-e2/-s/-s2: slic-p: 80 70 ? 105 90 130 110 ma ma loop current gain accuracy ?? ??3% loop current offset error 1) ? ? ?0.75 ? 0.75 ma loop open resistance tip to bgnd r tg modes: power down i t =2ma, t a =25c ?5 ?k ? loop open resistance ring to v bat r bg modes: power down i r =2ma, t a =25c ?5 ?k ? ring trip function ? ? ? ? ? ? ring trip dc voltag e ? slic-e/-e2/-s/-s2: slic-p: balanced slic-p: unbalanced 0 0 ? ? ? v batr /2 30 30 ? vdc vdc vdc
duslic electrical characteristics preliminary data sheet 342 ds3, 2003-07-11 6.3 duslic power up for power up of slicofi-2/-2s and slic devices please refe r to the instructions given in the device data sheets. 6.4 duslic timing characteristics t a = ?40 c to 85 c, unless otherwise stated. 6.4.1 input/output waveform for ac tests figure 83 waveform for ac tests during ac-testing, the cmos inputs are driv en at a low level of 0.8 v and a high level of 2.0 v. the cmos outputs are measured at 0.5 v and v dd ? 0.5 v respectively. ring trip detection time delay ? ? ? ? 2 cycle ring off time delay ? ? ? ? 2 cycle 1) can be reduced with current offset error compensation described in chapter 3.8.2.8 table 78 dc characteristics (cont?d) parameter symbol conditions limit values unit min. typ. max. ezm37010 test points 2.0 v 0.8 v v dd ? 0.5 v 2.0 v 0.8 v 0.5 v device under test c load = 50 pf max output pad: input pad: i ol , i oh device under test v il , v ih
duslic electrical characteristics preliminary data sheet 343 ds3, 2003-07-11 6.4.2 mclk/fsc timing figure 84 mclk/fsc-timing parameter symbol limit values unit min. typ. max. period mclk 1) 512 khz 100 ppm 1536 khz 100 ppm 2048 khz 100 ppm 4096 khz 100 ppm 7168 khz 100 ppm 8192 khz 100 ppm 1) the mclk frequency must be an integer multiple of the fsc frequency. t mclk 1952.93 650.98 488.23 244.116 139.495 122.058 1953.13 651.04 488.28 244.141 139.509 122.070 1953.32 651.11 488.33 244.165 139.523 122.082 ns mclk high time t mclkh 0.4 t mclk 0.5 t mclk 0.6 t mclk s period fsc 1) t fsc ? 125 ? s fsc setup time t fsc_s 10 50 ? ns fsc hold time t fsc_h 40 50 ? ns fsc (or pcm) jitter time ?0.2 t mclk ?+0.2 t mclk ns t mclk mclk fsc fsc_s t mclkh t t fsc_h fsc t 50% ezm35000
duslic electrical characteristics preliminary data sheet 344 ds3, 2003-07-11 6.4.3 pcm interface timing 6.4.3.1 single-clocking mode figure 85 pcm interface timi ng ? single-clocking mode parameter symbol limit values unit min. typ. max. period pclk 1) t pclk 1/8192 1/(n*64) with 2 n 128 1/128 ms pclk high time t pclkh 0.4 t pclk 0.5 t pclk 0.6 t pclk s period fsc 1) t fsc ? 125 ? s fsc setup time t fsc_s 10 50 ? ns fsc hold time 1 t fsc_h1 40 50 t fsc ? t pclk ? t fsc_s ns fsc hold time 2 t fsc_h2 40 50 ? ns dra/b setup time t dr_s 10 50 ? ns dra/b hold time t dr_h 10 50 ? ns t pclk pclk fsc dra/b dxa/b pclkh t high imp. t dr_s dr_h t t ddx ddxhz t fsc t tca/b dtcon t t dtcoff 50% fsc_s t t fsc_h1 t fsc_h2 ezm22013
duslic electrical characteristics preliminary data sheet 345 ds3, 2003-07-11 dxa/b delay time 2) t ddx 25 ? t ddx_min + 0.4[ns/pf] c load [pf] ns dxa/b delay time to high z t ddxhz 25 ? 50 ns tca/b delay time on t dtcon 25 ? t dtcon_min + 0.4 [ns/pf] c load [pf] ns tca/b delay time off t dtcoff 25 ? t dtcoff_min + 2 r pullup [ k ? ] c load [pf] ) ns 1) the pclk frequency must be an integer multiple of the fsc frequency. 2) all delay times are made up by two components: an intr insic time (min-time), caused by internal processings, and a second component caused by external circuitry ( c load , r pullup >1.5k ? ) parameter symbol limit values unit min. typ. max.
duslic electrical characteristics preliminary data sheet 346 ds3, 2003-07-11 6.4.3.2 double-clocking mode figure 86 pcm interface timi ng ? double-clocking mode t pclk pclk dxa/b pclkh t high imp. t ddx ddxhz t fsc t tca/b dtcon t t ddtcoff 50% dra/b t dr_s dr_h t fsc t fsc_h1 t fsc_h2 fsc_s t ezm22014
duslic electrical characteristics preliminary data sheet 347 ds3, 2003-07-11 parameter symbol limit values unit min. typ. max. period pclk 1) t pclk 1/8192 1/(n*64) with 4 n 128 1/256 ms pclk high time t pclkh 0.4 t pclk 0.5 t pclk 0.6 t pclk s period fsc 1) t fsc ?125? s fsc setup time t fsc_s 10 50 ? ns fsc hold time 1 t fsc_h1 40 50 t fsc ? t pclk ? t fsc_s ns fsc hold time 2 t fsc_h2 40 50 ? ns dra/b setup time t dr_s 10 50 ? ns dra/b hold time t dr_h 10 50 ? ns dxa/b delay time 2) t ddx 25 ? t ddx_min + 0.4[ns/pf] c load [pf] ns dxa/b delay time to high z t ddxhz 25 ? 50 ns tca/b delay time on t dtcon 25 ? t dtcon_min + 0.4[ns/pf] c load [pf] ns tca/b delay time off t dtcoff 25 ? t dtcoff_min + 2 r pullup [ k ? ] c load [pf] ) ns 1) the pclk frequency must be an integer multiple of the fsc frequency. 2) all delay times are made up by two components: an intrin sic time (min-time), caused by internal processings, and a second component caused by external circuitry ( c load , r pullup >1.5k ? )
duslic electrical characteristics preliminary data sheet 348 ds3, 2003-07-11 6.4.4 microcontroller interface timing figure 87 microcontroll er interface timing parameter symbol limit values unit min. typ. max. period dclk t dclk 1/8192 ? ? ms dclk high time t dclkh ?0.5 t dclk ? s cs setup time t cs_s 10 50 ? ns cs hold time t cs_h 30 50 ? ns din setup time t din_s 10 50 ? ns din hold time t din_h 10 50 ? ns dout delay time 1) 1) all delay times are made up by two components: an intrin sic time (min-time), caused by internal processings, and a second component caused by external circuitry ( c load ) t ddout 30 ? t ddout_min + 0.4[ns/pf] c load [pf] ns dout delay time to high z t ddouthz 30 ? 50 ns ezm22015 dclk cs din dout cs_s t high imp. t din_s din_h t t ddout t dclkh dclk t t cs_h 50% ddouthz t
duslic electrical characteristics preliminary data sheet 349 ds3, 2003-07-11 6.4.5 iom-2 interface timing 6.4.5.1 single-clocking mode figure 88 iom-2 interface ti ming ? single-clocking mode parameter symbol limit values unit min. typ. max. period dcl 1) 1) the dcl frequency must be an integer multiple of the fsc frequency. t dcl ? 1/2048 ? ms dcl high time t dclh 0.4 t dcl 0.5 t dcl 0.6 t dcl s period fsc 1) t fsc ? 125 ? s fsc setup time t fsc_s 10 50 ? ns fsc hold time 1 t fsc_h1 40 50 t fsc ? t dcl ? t fsc_s ns fsc hold time 2 t fsc_h2 40 50 ? ns dd setup time t dd_s 10 50 ? ns dd hold time t dd_h 10 50 ? ns du low time 2) t ddu_low 25 ? t ddu_low (min) + 0.4[ns/pf] c load [pf] ns du high time 2) t ddu_high 25 ? t ddu_high (min) + 2 r pull-up [k ? ] c load [pf] ns t dcl dcl du dclh t t ddu_low ddu_high t 50% fsc dd t dd_s dd_h t fsc fsc_s t t fsc_h1 t fsc_h2 t ezm22016
duslic electrical characteristics preliminary data sheet 350 ds3, 2003-07-11 2) du low and high times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry ( c load , r pullup >1.5k ? )
duslic electrical characteristics preliminary data sheet 351 ds3, 2003-07-11 6.4.5.2 double-clocking mode figure 89 iom-2 interface ti ming ? double-clocking mode parameter symbol limit values unit min. typ. max. period dcl 1) 1) the dcl frequency must be an integer multiple of the fsc frequency. t dcl ?1/4096? ms dcl high time t dclh 0.4 t dcl 0.5 t dcl 0.6 t dcl s period fsc 1) t fsc ?125? s fsc setup time t fsc_s 10 50 ? ns fsc hold time 1 t fsc_h1 40 50 t fsc ? t dcl ? t fsc_s ns fsc hold time 2 t fsc_h2 40 50 ? ns dd setup time t dd_s 10 50 ? ns dd hold time t dd_h 10 50 ? ns du low time 2) 2) du low and high times are made up by two component s: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry ( c load , r pullup >1.5k ? ) t ddu_low 25 ? t ddu_low (min) + 0.4[ns/pf] c load [pf] ns du high time 2) t ddu_high 25 ? t ddu_high (min) + 2 r pull-up [k ? ] c load [pf] ns t dcl dcl du dclh t 50% fsc t dd t dd_s dd_h t fsc t fsc_h1 t fsc_h2 fsc_s t t ddu_low ddu_high t ezm22017
duslic application circuits preliminary data sheet 352 ds3, 2003-07-11 7 application circuits application circuits are show n for internal ringing with duslic-e/-e2/-s/-p (balanced and unbalanced) and for extern al unbalanced ringi ng with duslic-e/-e2/-s/-s2/-p for one line. channel a and the slic must be dupl icated in the circuit diagrams to show all necessary components for two channels. 7.1 internal ringing (balanced/unbalanced) internal balanced ringing is supported up to 85 vrms for duslic-e/-e2/-p and up to 45 vrms for duslic-s. internal unbalanced ringing is support ed for slic-p with ringing amplitudes up to 50 vrms without any a dditional components. all duslic chip sets incorporate internal off-hook - and ring trip detection.
duslic application circuits preliminary data sheet 353 ds3, 2003-07-11 7.1.1 circuit diagrams internal ringing (balanced & unbalanced) figure 90 internal (balanced and unbalanced) ringing with slic-p acpa acna dcpa dcna c1a c2a cdcna cdcpa itaca ita vcmita ila vcm vcms c dc slicofi-2 slicofi-2s only channel a and slic interface pins connected for this example c itaca c vcmita r it1a slic-p r it2a r ila acp acn dcp dcn c1 c2 vcms il it bgnd agnd cext bgnd agnd agnd c ext ring tip channel a peb 4266 peb 3265 peb 3264 c3 v dd v batr v batl c 1 bgnd v bath bgnd v batr agnd v dd c 1 c 1 d 2 d 2 d 1 c 1 bgnd v batl d 2 d 1 d 1 v bath r stab 30 ? r stab 30 ? tip ring u1 r prot 20 ? fuseable resistor tip ring c stab r prot 20 ? fuseable resistor bgnd c stab overvoltage protection io 2a crefab gndab gnda gndd gndpll agnd agnd agnd c ref agnd v dda v ddr v ddd v ddpll c 1 agnd c 1 agnd c 1 agnd c 1 agnd v cca v cca v cca v cca c 2 pcm / c interface io m -2 interface ezm20004a2
duslic application circuits preliminary data sheet 354 ds3, 2003-07-11 figure 91 internal (balanced) ringi ng with slic-e/-e2 or slic-s/-s2 acpa acna dcpa dcna c1a c2a cdcna cdcpa itaca ita vcmita ila vcm vcms c dc slicofi-2 slicofi-2s only channel a and slic interface pins connected for this example c itaca c vcmita r it1a slic-e/-e2 slic-s/-s2 r it2a r ila acp acn dcp dcn c1 c2 vcms il it bgnd agnd cext bgnd agnd agnd c ext ring tip channel a peb 4265/-2 peb 4264/-2 r stab 30 ? r stab 30 ? tip 1) ring 1) u1 r prot 20 ? fuseable resistor tip ring c stab r prot 20 ? fuseable resistor bgnd peb 3265 peb 3264 c stab overvoltage protection v hr v dd v bath v batl c 1 bgnd v batl bgnd v bath agnd v dd bgnd v h c 1 c 1 c 1 d 2 d 2 d 1 crefab gndab gnda gndd gndpll agnd agnd agnd c ref agnd v dda v ddr v ddd v ddpll c 1 agnd c 1 agnd c 1 agnd c 1 agnd v cca v cca v cca v cca c 2 pcm / c interface iom -2 interface ezm20004a11
duslic application circuits preliminary data sheet 355 ds3, 2003-07-11 as figure 90 shows, balanced and unba lanced internal ringing use the same line circuit. 7.1.2 bill of materials table 79 shows the external passive componen ts needed for a dua l-channel solution consisting of one sl icofi-2/-2s and two sl ic-e/-e2/-s/-s2/-p. to handle higher electromagnetic compatibil ity (emc) requirements , additional effort in the circuit design may be necessary, such as a current-compensated choke of 470 h in the tip/ring lines. as well as the c 1 capacitors, one 22 f capacitor per 8 tip/ring lines is recommended for buff ering the supply voltages. table 79 external components in applic ation circuit duslic-e/-e2/-s/-s2/-p no. symbol value unit relat. tol. rating 2 r it1 470 ? 1% 2 r it2 680 ? 1% 2 r il 1.6 k ? 1% 4 r stab 30 ? 1% 1) 1) matching tolerance dependent on longitudinal balance requirements (for details see the application note external components ). 4 r prot 2) 2) see application note protection of duslic / vinetic linecard chip sets against overvoltages and overcurrents . 20 ? 1% 1) 4 c stab 15 (typ.) nf 10 % 100 v 2 c dc 120 nf 10 % 10 v 2 c itac 680 nf 10 % 10 v 2 c vcmit 680 nf 10 % 10 v 1 c ref 68 nf 20 % 10 v 2 c ext 470 nf 20 % 10 v 12 c 1 100 (typ.) nf 10 % 1 c 2 3) 3) as close as possible connected to v ddd and gndd at slicofi-2 4.7 f 20 % 10 v, tantal ? d 1 4) 4) optional; recommended only if power supply relation v batr < v bath < v batl can not be guaranteed. bas21 ? ? ? 4 d 2 bas21 ? ? ? 2 u 1 2) overvoltage protection element ?? ?
duslic application circuits preliminary data sheet 356 ds3, 2003-07-11 7.2 external unbalanced ringin g with duslic-e/-e2/-s/-s2/-p external unbalanced ringing appl ication circuits are shown for a standard solution (see figure 92 and figure 93 ) and for a solution dedicated to higher loop lengths (see figure 94 and figure 95 ). note: only the codec/slic combinations shown in table 3 "duslic chip sets presented in this data sheet" on page 20 are possible.
duslic application circuits preliminary data sheet 357 ds3, 2003-07-11 7.2.1 circuit diagrams external unbalanced ringing figure 92 external unbalanced ringi ng with slic-e/-e2 or slic-s/-s2 fsc dcl/pclk dd/drb du/dout ts0/din ts1/dclk ts2/cs mclk sel24/dra dxa dxb rsync acpa acna dcpa dcna c1a c2a cdcna cdcpa itaca ita vcmita ila vcm vcms cref gndr test c dc slicofi-2 sli cofi -2s (channel a, b) c itaca c vcmita r it1a sli c-e/ -e2 sli c-s/ -s2 r it2a r ila acp acn dcp dcn c1 c2 gnda gndd gndpll agnd agnd agnd c ref vcms agnd il it bgnd agnd cext bgnd agnd agnd c ext ring tip channel a peb 4265/-2 peb 4264/-2 peb 3265 peb 3264 io1a io3a io4a io1b io2b io3b io4b io2a reset tcb tca int pcm/iom-2 agnd selclk agnd v hr v dd v bath v batl c 1 bgnd v batl bgnd v bath agnd v dd bgnd v hr c 1 c 1 c 1 d 2 d 2 d 1 c 1 agnd c 1 agnd c 1 agnd c 1 agnd v cca v cca v cca v cca c 2 v dda v ddr v ddd v ddpll r stab 30 ? r stab 30 ? tip ring u1 r prot 20 ? fuseable resistor tip ring c stab r prot 20 ? fuseable resistor bgnd c stab overvoltage protection pin rsync slicofi-2/-2s + 5 v 1 n 4 1 4 8 5.1 k ? 22 k ? external ring generator ezm14044
duslic application circuits preliminary data sheet 358 ds3, 2003-07-11 figure 93 external unbala nced ringing with slic-p in the circuits shown in figure 92 and figure 93 the ring current is sensed on only one line (tip line). it is theref ore restricted to applications with low longitudinal influence (short lines). fsc dcl/pclk dd/drb du/dout ts0/din ts1/dclk ts2/cs mclk sel24/dra dxa dxb rsync acpa acna dcpa dcna c1a c2a cdcna cdcpa itaca ita vcmita ila vcm vcms cref gndr test c dc sli cofi -2 slicofi-2s (channel a, b) c itaca c vcmita r it1a sli c-p r it2a r ila acp acn dcp dcn c1 c2 gnda gndd gndpll agnd agnd agnd c ref vcms agnd il it bgnd agnd cext bgnd agnd agnd c ext ring tip ch an n el a peb 4266 peb 3265 peb 3264 io1a io3a io4a io1b io2b io3b io4b io2a reset tcb tca int pcm/iom-2 c3 * agnd selclk agnd connected to io2a * optional c 1 agnd c 1 agnd c 1 agnd c 1 agnd v cca v cca v cca v cca c 2 v dd v batr v batl v bath v dda v ddr v ddd v ddpll r stab 30 ? r stab 30 ? tip ring u1 r prot 20 ? fuseable resistor tip ring c stab r prot 20 ? fuseable resistor bgnd c stab overvoltage protection pin rsync slicofi-2/-2s + 5 v 1 n 4 1 4 8 5.1 k ? 22 k ? external ring generator c 1 bgnd v bath bgnd v batr agnd v dd c 1 c 1 d 2 d 2 d 1 c 1 bgnd v batl d 2 d 1 d 1 ezm14044p
duslic application circuits preliminary data sheet 359 ds3, 2003-07-11 figure 94 external unb. ringing (long loops) with sl ic-e/-e2 or slic-s/-s2 ezm35003 pcm/iom-2 fsc dcl/pclk dd/drb du/dout ts0/din ts1/dclk ts2/cs int mclk sel24/dra dxa dxb tca tcb rsync acpa acna dcpa dcna c1a c2a cdcna cdcpa itaca ita vcmita ila vcm vcms cref gndr reset test c dc sli cofi -2 sli cofi -2s (channel a, b) c itaca c vcmita r it1a sli c-e/ -e2 sli c-s/ -s2 r it2a r ila acp acn dcp dcn c1 c2 gnda gndd gndpll agnd agnd agnd c ref vcms agnd il it bgnd agnd cext bgnd agnd agnd c ext chann el a peb 3265 peb 3264 peb 4265/-2 peb 4264/-2 vcms of slicofi-2/-2s io3a or io4a of slicofi-2/-2s zero cr ossi ng si gnal ( ttl l evel) rsync of slicofi- 2/- 2s io1a io3a io4a io1b io2b io3b io4b agnd selclk agnd v hr v dd v bath v batl c 1 bgnd v batl bgnd v bath agnd v dd bgnd v hr c 1 c 1 c 1 d 2 d 2 d 1 c 1 agnd c 1 agnd c 1 agnd c 1 agnd v cca v cca v cca v cca c 2 v dda v ddr v ddd v ddpll ring tip r stab 30 ? u1 r prot 20 ? fuseable resistor tip ring c stab r prot 20 ? fuseable resistor bgnd c stab overvoltage protection r stab 30 ? + 68 k ? 68 k ? ring generator ? 48 vdc 80 v rms ri ng tip - 150 ? 2 m ? 150 ? 2 m ? 2 m ? 2 m ? lm358 relay + 5v 1 n 4 1 4 8 5.1 k ? 22 k ? io1a of slicofi-2/-2s
duslic application circuits preliminary data sheet 360 ds3, 2003-07-11 figure 95 external unbalanced ringing (long loops) with slic-p ezm35003p pcm/iom-2 fsc dcl/pclk dd/drb du/dout ts0/din ts1/dclk ts2/cs int mclk sel24/dra dxa dxb tca tcb rsync acpa acna dcpa dcna c1a c2a cdcna cdcpa itaca ita vcmita ila vcm vcms cref gndr reset test c dc slicofi-2 sli cofi -2s (channel a, b) c itaca c vcmita r it1a sli c-p r it2a r ila acp acn dcp dcn c1 c2 gnda gndd gndpll agnd agnd agnd c ref vcms agnd il it bgnd agnd cext bgnd agnd agnd c ext chan nel a peb 3265 peb 3264 peb 4266 io1a io3a io4a io1b io2b io3b io4b c3 * agnd selclk agnd connected to io2a v dd v batr v batl v bath c 1 agnd c 1 agnd c 1 agnd c 1 agnd v cca v cca v cca v cca c 2 v dda v ddr v ddd v ddpll * optional vcms of slicofi-2/-2s io3a or io4a of slicofi-2/-2s zer o cr ossi ng si gnal ( ttl l evel ) rsync of slicofi- 2/- 2s ring tip r stab 30 ? u1 r prot 20 ? fuseable resistor tip ring c stab r prot 20 ? fuseable resistor bgnd c stab overvoltage protection r stab 30 ? + 68 k ? 68 k ? ring generator ? 48 vdc 80 v rms ri ng tip - 150 ? 2 m ? 150 ? 2 m ? 2 m ? 2 m ? lm358 relay + 5v 1 n 4 1 4 8 5.1 k ? 22 k ? io1a of slicofi-2/-2s c 1 bgnd v bath bgnd v batr agnd v dd c 1 c 1 d 2 d 2 d 1 c 1 bgnd v batl d 2 d 1 d 1
duslic application circuits preliminary data sheet 361 ds3, 2003-07-11 in the circuits shown in figure 94 and figure 95 the ring current is sensed in both tip and ring lines. longitudinal influence is cancelled out. this circuit therefore is recommended for long line applications. 7.3 duslic layout recommendations for each of the supply pins of slicofi-2x and slic, 100 nf capacitors should be used. these capacitors should be placed as close as possibl e to the supply pin of the associated ground/supply pins. slicofi-2x and slic should be placed as close to each other as possible. slicofi-2x and slic should be pl aced in such way that lines acp, acn, dcp, dcn, it, itac are as short as possible. acp/acn lines should be placed in para llel and symmetrical; co nnections via holes should be avoided. acp/acn lines should be run above a gnd plane; dcp/dcn lines should be placed in parall el and symmetrical; connections via holes should be avoided. dcp/dcn lines should be run above a gnd plane vcmita and vcm shoul d be connected directly (vcmita via c vcmita ) at resistor r it2a (680 ? ). vcmitb and vcm shoul d be connected directly (vcmitb via c vcmitb ) at resistor r it2b (680 ? ). use separate traces for connec ting vcm/vcmita and vcm/vcmitb; these two vcm traces should be con nected directly at the vcm pin of slicofi-2x in case of a multilayer board, it is re commended to use one common ground layer (agnd, bgnd, gndd, gnda, gndb, gndpll connected together and share one ground layer). in case of a two-layer board, a common ground should be us ed for agnd, bgnd, gndd, gnda, gndb and gndpll. ground trac es should be laid out as large as possible. connections to and from ground pins should be as short as possible. any unused area of the board should be filled with gr ound (copper pouring). the connection of gnd, v h and v bat to the protection de vices should be low- impedance in order to avoid such issues as a gnd shift due to the high impulse currents in case of an overvoltage strike. tip/ring traces from the slic should be symmetrical.
duslic application circuits preliminary data sheet 362 ds3, 2003-07-11 figure 96 duslic lay out recommendation slic a slic b slico fi-2x acna acpa dcnb dcpb itaca vcmita ita vcm itb vcmitb itacb dcpb dcnb acnb acpb parallel/symmetrical as short as possible no via holes, should run above a gnd plane parallel/symmetrical as short as possible no via holes, should run above a gnd plane connection directly at resistor connection directly at slicofi-2 il-a it-a it-b il-b r ila r it1a r it2a r ilb r it2b r it1b c vcmita c vcmitb layout_r
duslic package outlines preliminary data sheet 363 ds3, 2003-07-11 8 package outlines figure 97 slic-s/-s2, slic -e/-e2, slic-p (peb 426x) note: the p-dso-20-5 package is designed with heatsink on top. the pi n counting for this package is clockwise (top view). attention: the heatsink is connected to v bath (v batr ) via the chip substrate. due to the high voltage of up to 150 v between vhr and v bath (b gnd and v batr ), touching of the heatsink or any attached conducting part can be hazardous. p-dso-20-5 (plastic dual small outline) gps05755 top view smd = surface mounted device dimensions in mm you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products .
duslic package outlines preliminary data sheet 364 ds3, 2003-07-11 figure 98 slic-s/-s2, slic-e /-e2, slic-p (peb426x) attention: the exposed die pad and die pad edges are connected to v bath (v batr ) via the chip substrate. due to the high voltage of up to 150 v between v hr and v bath (v batr and b gnd ), touching of the die pad or any attached conducting part ca n be hazardous. p-vqfn-48-4 (very thin profile quad flatpack no-lead) gvq09350 top view exposed die pad die pad edge smd = surface mounted device dimensions in mm you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products .
duslic package outlines preliminary data sheet 365 ds3, 2003-07-11 figure 99 tslic-s (peb 4364) attention: the heatslug is connected to v bath via the chip substrate. due to the high voltages of up to 90 v between v hra (vhrb) and v bath , touching of the heatslug or any attached conducting part can be hazardous. bottom view does not include plastic or metal protrusion of 0.15 max. per side 1 18 0.25 0.1 1.1 36 +0.13 0.25 36x 19 m (heatslug) 15.74 0.65 0.1 c ab 19 c 3.25 3.5 max. +0.1 0 0.1 0.1 36 2.8 b 11 0.15 1) 1.3 5? 0.25 3? -0.0 2 +0.07 6.3 14.2 (mold) 0.3 b 0.15 0.25 heatslug 0.95 heatslug 0.1 5.9 3.2 (metal) 0.1 (metal) 13.7 (metal) 10 1 -0.2 index marking (mold) 15.9 1) 0.1 a 1 x 45? 1) p-dso-36-15 (plastic dual small outline) gps09181 top view smd = surface mounted device dimensions in mm you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products .
duslic package outlines preliminary data sheet 366 ds3, 2003-07-11 figure 100 tslic-e (peb 4365) attention: the heatslug is connected to v bath via the chip substrate. due to the high voltages of up to 150 v between v hra (v hrb ) and v bath , touching of the heatslug or any attached conducting part ca n be hazardous. bottom view does not include plastic or metal protrusion of 0.15 max. per side 1 18 0.25 0.1 1.1 36 +0.13 0.25 36x 19 m (heatslug) 15.74 0.65 0.1 c ab 19 c 3.25 3.5 max. +0.1 0 0.1 0.1 36 2.8 b 11 0.15 1) 1.3 5? 0.25 3? -0.0 2 +0.07 6.3 14.2 (mold) 0.3 b 0.15 0.25 heatslug 0.95 heatslug 0.1 5.9 3.2 (metal) 0.1 (metal) 13.7 (metal) 10 1 -0.2 index marking (mold) 15.9 1) 0.1 a 1 x 45? 1) p-dso-36-10 (plastic dual small outline) gps09181 top view smd = surface mounted device dimensions in mm you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products .
duslic package outlines preliminary data sheet 367 ds3, 2003-07-11 figure 101 slicofi-2x (peb 3265, peb 3264) p-mqfp-64-1 (plastic metric qu ad flat package) gpm05250 top view smd = surface mounted device dimensions in mm you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products .
duslic package outlines preliminary data sheet 368 ds3, 2003-07-11 figure 102 slicofi-2x (peb 3265, peb 3264) p-tqfp-64-1 (plastic thin quad flat package) gpm05250 top view smd = surface mounted device dimensions in mm you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products .
duslic terminology preliminary data sheet 369 ds3, 2003-07-11 9 terminology a acth active with v bath actl active with v batl actr active with v batr or v hr and v bath adc analog digital converter ar attenuation receive ax attenuation transmit b bp band-pass c cmp compander codec coder decoder cop coefficient operation cram coefficient ram d dac digital analog converter dsp digital signal processor dup data upstream persistence counter duslic dual channel subscrib er line interface concept duslicos dual channel subscriber line interface concept coefficients software e exp expander f frr frequency respons e receive filter frx frequency response transmit filter l lssgr local area transport acce ss switching system generic requirements p pcm pulse code modulation
duslic terminology preliminary data sheet 370 ds3, 2003-07-11 pdh power down high impedance pdrhl power down load resistive with v bath and bgnd pdrrl power down l oad resisitve with v batr and bgnd pdrh power down resistive with v bath and bgnd pdrr power down resistive with v batr and bgnd pofi post filter prefi antialiasing pre filter r rect rectifier (testloops, levelmetering) s slic subscriber line interface ci rcuit (same for all versions) slic-s/-s2 subscriber line interf ace circuit stan dard feature set peb 4264/-2 slic-e/-e2 subscriber line interface circuit enhanced feature set peb 4265/-2 slic-p subscriber line interface ci rcuit enhanced power management peb 4266 slicofi-2x dual channel subscriber li ne interface codec filter (same for all versions) slicofi-2 dual chan nel subscriber line interface codec filter peb 3265 slicofi-2s dual channel subscriber line interface codec filter peb 3264 sop status operation t tg tone generator th transhybrid balancing thfix transhybrid balancing filter (fixed) ts time slot tslic-s twin subscriber line inte rface circuit standard feature set peb 3264 tslic-e twin subscriber line inte rface circuit standard feature set peb 3265 ttx teletax
duslic index preliminary data sheet 371 ds3, 2003-07-11 10 index numerics 170v technology 45 a active 90 active high 74, 76, 78, 80, 82 active low 74, 76, 78, 80, 82 active ring 74, 76, 78, 80, 83 active state 52, 92 active with hir 74, 77, 79, 81, 83 active with hit 74, 77, 79, 81, 83 active with metering 75, 77, 141, 260, 320 b balanced ringin g 46, 352 battery feed 29 c caller id 23, 30, 59, 66, 157 central office 24 coding 29 constant current zone 35 constant voltag e zone 37 cop-command 141, 142, 203, 315 cram coefficients 205, 318 d dc characteristic 38 digital loop carrier 24 dtmf 30, 66, 155, 177, 179, 295 dtmf decoder 30 dtmf generator 23, 30, 56 duslicos 30, 203, 315 e enhanced digital signal processor 56, 151, 157 mips requirements 66 pop commands 207 external components duslic-p 355 external conference 71 external ringing 48, 94, 170, 290 f fiber in the loop 24 first command byte 140, 262, 263, 322, 323 frequency response 29, 327 fsk 30 g ground key 152 ground start 77 h hybrid 29 hybrid balance 29 i impedance matching 29 intelligent nt 24 internal conference 71 iom-2 interface 1 22, 129, 260, 263, 320, 323 isdn terminal adapters 24 l layout recommen dation 361 levelmeter ac 105 dc 100 ttx 108 lin mode 72 lin16 mode 73 line echo cancellation 30, 63, 66, 178 pop commands 229 line resistance 113 line testing 94 m message waiting 23, 67
duslic index preliminary data sheet 372 ds3, 2003-07-11 metering 23, 54, 1 81, 183, 185, 297, 299, 301 microcontroller inte rface 122, 127 monitor channel op eration 133 monitor receiver 136 monitor transfer pr otocol 133 monitor transmitter 135 o operating modes cidd byte slicofi-2 260 cidd byte slicofi-2s 320 ciop byte 141 duslic 74 duslic-e/-e2 80 duslic-p 82 duslic-s/-s2 78 power management 90 overvoltage protection 29 p pcm channel 126 pcm interface 43, 122, 150, 153, 272, 275, 344 pcm mode 72, 88, 189, 193, 305, 307 pcm/c interface 72, 122, 173, 292 pcm16 mode 73 pcm-active 71 pcm-off 71 polarity reversal 23, 55 pop command 142, 207 power dissipation operating modes 90 slic 91 slic output stage 39 slicofi-2 91 power down 90 , 141, 167, 260, 320 power down high impe dance 74, 76, 141, 172, 260, 291, 320 power down resistive 74, 76, 78, 80, 82 power down state 53, 71, 91, 197, 199, 309, 311 power management 20, 23, 76, 90 private branch exchange 24 r ramp generator 68, 79, 81, 83 read command 127 receive gain 29 receive path 43 , 178, 197, 199, 201, 309, 311, 313 register description example 142 reset 84, 141 status 154, 276 resistive zone 36 ring on ring 77 ring on tip 77 ring pause 75, 77, 79, 81, 83 ring trip 45, 77, 341 ringer equivalence number 45 ringing 29, 45, 74 , 77, 79, 81, 83, 90, 141, 260, 320 s second command byte 127, 142, 262, 263, 322, 323 signaling 29 , 52, 58, 263, 323 sleep 74, 75, 80, 82, 141, 260, 320 soft reversal 55, 170, 290 sop-command 141, 144, 266 supervision 29, 52 t teletax metering 30 test loops 119 three-party conferen cing 68, 173 time slot assignme nt 43, 132 tip/ring interface 122, 139 transmit gain 29, 328 transmit path 43, 178, 197, 199, 201, 309, 311, 313 ttx 29, 54, 77, 170, 199, 204 , 311, 317 u unbalanced ringing 46, 90, 167, 287 universal tone detectio n 30, 65, 66, 156
duslic index preliminary data sheet 373 2003-07-11 pop commands 250 universal tone de tection 177 v voice over packet network 24 voltage reserve 34, 40 w wireless local loop 24 write command 127
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